Achronix Speedster22i PCIe - Manual (Page 11)

UG030, April 26, 2013 11

Ordering is maintained separately for internal DMA Register and AXI
destinations

The completion of a read request to the same destination (DMA
Registers or AXI) can be used to guarantee that prior writes to the
same destination have completed

Reads are blocked until all writes occurring before the read have fully
completed; for AXI, a write is completed when it returns a completion
response on the Write Response Channel; for internal DMA Registers,
a write is completed when it is written into the DMA Registers such
that a following read will return the new value

Supports full duplex bandwidth utilization when being driven by a
remote PCI Express DMA Master

Supports multiple simultaneously outstanding write and read requests

Utilizes maximum 16 beat bursts for compatibility with AXI3
and AXI4