Achronix Speedster22i PCIe - Manual (Page 63)

UG030, April 26, 2013 63
Field Name Default Values Description Verilog Parameter
Equalization
Method Preset Preset,
Algorithm,
Table CFG_8G_CONSTANTS_
EQ_METHOD
2’b00 – Preset, 2’b01 –
Algorithm, 2’b10 – Table
Equalization
TS1 Ack
Delay 256 1-256 Defines how long the upstream
port (Phase 2) or downstream
port (Phase 3) waits after
requesting new
coefficients/presets before looking
for incoming EQ TS1 sets from
the remote link partner. This
delay by specification should be
set to the round trip delay to the
remote link partner (including
logic delays in the requesting
port) + 500ns. The delay used will
be equal to (eq_ts1_ack_delay[7:0]
* 16) + 500 ns. If eq_ts1_ack_delay
is set to 0, then this will be equal
to a maximum setting of 256, or
256*16 + 500 ns = 4.6 CFG_8G_CONSTANTS_
EQ_TS1_ACK_DELAY.