Achronix Speedster22i PCIe - Manual (Page 30)

UG030, April 26, 2013 30
Port Name Direction Clock Description
are decoded differently for
Completion versus Base Address
Region hits

Bits[8:0] –
o If Completion TLP (Bit[9] == 1)
 Bits[8] - Reserved
 Bits[7:0] – Tag; the
Requestor Tag
contained in the TLP;
use to route
completions to the
associated requestor
logic; this field is
reserved if the TLP is a
message rather than a
completion
o If Base Address Region TLP
(Bit[9] == 0)
 Bit[8] – When (1), the
packet is a “write”
transaction; when (0),
the packet is a “read”
transaction
 Bit[7] – When (1), the
packet requires one or
more Completion
transactions as a
response; (0)
otherwise
 Bit[6] – (1) if the TLP
targets the Expansion
ROM Base Address
region
 Bit[5] – (1) if the TLP
targets Base Address
Region 5
 Bit[4] – (1) if the TLP
targets Base Address
Region 4
 Bit[3] – (1) if the TLP
targets Base Address
Region 3
 Bit[2] – (1) if the TLP
targets Base Address
Region 2
 Bit[1] – (1) if the TLP