Achronix Speedster22i PCIe User Manual
Page 32
UG030, April 26, 2013
32
Port Name
Direction
Clock
Description
mgmt_cfg_status[1183] (MSI-X Enable):
MSI-X_Enable==1 : MSI-X
Interrupt Mode
MSI_Enable ==1 : MSI Interrupt
Mode
MSI-X_Enable == 0 & MSI_Enable
== 0 : Legacy Interrupt Mode
Note: It is illegal for software to set both MSI-
X_Enable and MSI_Enable at the same time.
User’s task: User interrupt logic must behave
differently depending upon the value of MSI-
X_Enable and MSI_Enable and whether the
core is a Single or Multiple Interrupt
Configuration:
Single Interrupt Configuration
When Legacy Interrupt Mode is
enabled (MSI_Enable == 0),
mgmt_interrupt implements one level-
sensitive interrupt (INTA, INTB,
INTC, or INTD as selected by
mgmt_cfg_constants[132:131]). All
interrupt sources should be logically
ORed together to generate
mgmt_interrupt. Each interrupt source
should continue to drive a 1 until it has
been serviced and cleared by software
at which time it should switch to
driving 0. The core monitors high and
low transitions on mgmt_interrupt and
sends an Interrupt Assert message on
each 0 to 1 transition and an Interrupt
De-Assert Message on each 1 to 0
transition. Transitions which occur too
close together to be independently
transmitted are merged.
When MSI Interrupt Mode is enabled
(MSI_Enable == 1), mgmt_interrupt is
used to implement one MSI Message.
An MSI Interrupt Message is
generated each time mgmt_interrupt
transitions from 0 to 1. To promote
sharing of mgmt_interrupt among
several interrupt sources, each source
should assert mgmt_interrupt for a
single clock cycle and all sources