Achronix Speedster22i PCIe - Manual (Page 39)

UG030, April 26, 2013 39
Pin Name Direction Clock Description
multiple AXI transfers), that provides the
UserControl[63:0] value software placed in the first
Descriptor of the packet. Optional signal which may be
used to pass information on a per packet basis from user
software to user hardware; s2c_wusercontrol is only
valid for FIFO DMA
Addressable DMA: Write Data Channel implements
AXI3/AXI4 Master protocol; s2c_wusereop is a non-
standard AXI signal, with same timing as s2c_wlast, that
when 1 indicates that this is the final data transfer of a
DMA packet transfer
s2c_bvalid [1:0] Input s2c_aclk FIFO DMA: Write Response Channel is unused; tie
s2c_bready == 1 and ignore s2c_b* outputs
Addressable DMA: Write Response Channel; space is
reserved in the master to receive response from all
outstanding write requests, so t_bready is always 1 and
need not be used
s2c_bready [1:0] Output s2c_aclk
s2c_bresp [3:0] Input s2c_aclk
Card-to-System Engine Interface
Table 7: Card-to-System Interface Port Descriptions
Pin Name Direction Clock Description
c2s_areset_n [1:0] Output c2s_aclk Active-low asynchronous assert, c2s_aclk synchronous
de-assert reset; asserted when the DMA Engine has been
reset by software or by PCI Express reset
c2s_aclk [1:0] Input c2s_aclk AXI interface clock; may be a different clock than the
clock used on the PCI Express-side of the AXI DMA
Back-End Core; synchronization techniques are used to
enable support for a wide variety of clock rates
c2s_fifo_addr_n
[1:0] Input c2s_aclk Interface AXI Protocol Selection:

1 – FIFO DMA using AXI4-Stream Protocol

0 – Addressable DMA using AXI3/AXI4
Protocol
This port selects the interface protocol and affects the
operation of the remaining ports
c2s_arvalid [1:0] Output c2s_aclk FIFO DMA: Read Address Channel is unused; tie
c2s_arready == 1 and ignore c2s_ar* outputs
Addressable DMA: Read Address Channel; Optional
AWBURST, AWLOCK, AWCACHE, AWPROT are not
implemented; AWBURST is always incrementing-
address burst; cache, protected, and exclusive accesses
not supported
c2s_arready [1:0] Input c2s_aclk
c2s_araddr [71:0] Output c2s_aclk
c2s_arlen [7:0] Output c2s_aclk
c2s_arsize [5:0] Output c2s_aclk