Achronix Speedster22i PCIe - Manual (Page 75)

UG030, April 26, 2013 75
input [7:0] pcie_refclk_n ; //// FOR (N-SIDE)
input [7:0]
rx_p ; //// FOR (P-SIDE)
input [7:0] rx_n ; //// FOR (N-SIDE)
input [7:0]
i_serdes_sbus_req ;
input [15:0] i_serdes_sbus_data ;
///// REGULAR PARALLEL INTERFACE WITH FABRIC-CORE /////
input
i_sbus_clk ;
input i_sbus_sw_rst ;
input i_sbus_req ;
input [1:0] i_sbus_data ;
input
bypass_clk ;
input bypass_rst_n ;
input bypass_tx_valid ;
input bypass_tx_sop ;
input bypass_tx_eop ;
input [127:0] bypass_tx_data ;
input [15:0] bypass_tx_data_valid ;
input bypass_rx_ready ;
input bypass_interrupt ;
input bypass_interrupt_msix_req ;
input [127:0] bypass_interrupt_msix_vector ;
input bypass_enable ;
////// DMA INTERFACE ///
///// SYSTEM2CARD ////
input [1:0]
s2c_aclk ;
input [1:0] s2c_fifo_addr_n ;
input [1:0] s2c_awready ;
input [1:0] s2c_wready ;
input [1:0] s2c_bvalid ;
input [3:0] s2c_bresp ;
///// CARD2SYSTEM INTERFACE ////
input [1:0]
c2s_aclk ;
input [1:0] c2s_fifo_addr_n ;
input [1:0] c2s_arready ;
input [1:0] c2s_rvalid ;
input [255:0] c2s_rdata ;
input [3:0] c2s_rresp ;
input [1:0] c2s_rlas t ;
input [31:0] c2s_ruserstrb ;