Achronix Speedster22i PCIe - Manual (Page 33)

UG030, April 26, 2013 33
Port Name Direction Clock Description
should be ORed together onto
mgmt_interrupt. 0 to 1 transition
events which occur too close together
to be independently transmitted are
merged together into one MSI
message.
Multiple Interrupt Configuration

When Legacy Interrupt Mode is
enabled (MSI-X_Enable == 0 &
MSI_Enable == 0), mgmt_interrupt
implements one level-sensitive
interrupt (INTA, INTB, INTC, or INTD
as selected by
mgmt_cfg_constants[132:131]). All
interrupt sources should be logically
ORed together to generate
mgmt_interrupt. Each interrupt source
should continue to drive a 1 until it has
been serviced and cleared by software
at which time it should switch to
driving 0. The core monitors high and
low transitions on mgmt_interrupt and
sends an Interrupt Assert message on
each 0 to 1 transition and an Interrupt
De-Assert Message on each 1 to 0
transition. Transitions which occur too
close together to be independently
transmitted are merged.

When MSI-X or MSI Interrupt Mode is
enabled (MSI-X_Enable == 1 or
MSI_Enable == 1), mgmt_interrupt is
not used and MSI-X/MSI interrupts are
signaled on mgmt_interrupt_msix_req,
mgmt_interrupt_msix_ack, and
mgmt_interrupt_msix_vector instead.
bypass_msi_en Output bypass_clk MSI interrupt enable
bypass_msix_en Output bypass_clk MSI-X interrupt enable
bypass_interrupt_msix_req Input bypass_clk mgmt_interrupt_msix_req,
mgmt_interrupt_msix_ack, and
mgmt_interrupt_msix_vector are used to
signal MSI-X and MSI interrupts when the
MSI-X/Multi-Vector MSI Configuration core
option is present.
To request an MSI-X or MSI interrupt message
to be transmitted, mgmt_interrupt_msix_req is