Achronix Speedster22i PCIe - Manual (Page 47)

UG030, April 26, 2013 47
Field Name Default Values Description Verilog Parameter
Downstream Switch Port). When
the core is operating as an
Upstream Port (Endpoint,
Upstream Switch Port), the core
captures its Requestor/Completer
ID from received Configuration
Write transactions.
DMA
Bypass Disable Enable,
Disable Bypass DMA interface and use
only bypass interface No parameter. Wrapper
changes only. Tie
bypass_enable to 1’b1 if
Enable and show
bypass_* ports, else tie to
0 and hide bypass_*
interface. Also, other
ports m_*, t_*, s2c_* and
c2s_* ports should be
hidden if Enable, shown
if Disable.
Memory Map
BAR0 Base 0xFFFF0 A 32-bit Memory BAR uses one CFG_CONSTANTS_BAS