Achronix Speedster22i PCIe - Manual (Page 3)

UG030, April 26, 2013 3
Table of Contents
Copyright Info .................................................................................. 2
Table of Contents ............................................................................ 3
Table of Figures .............................................................................. 5
Introduction ..................................................................................... 6
Design Overview ............................................................................. 8
Major Interfaces ............................................................................. 10
AXI Target Interface ........................................................................................ 10
Target Only Design ................................................................................................ 13
AXI Back-End DMA Interface .......................................................................... 13
Addressable FIFO DMA ......................................................................................... 13
Packet DMA Descriptor Format ............................................................................. 15
Card-to-System Descriptor Field Descriptors ................................................................... 16
System-to-Card Descriptor Field Descriptors ................................................................... 18
AXI Master Interface........................................................................................ 20
DMA Bypass Interface ........................................................................................... 22
Transmit Interface ........................................................................................... 22
Receive Interface ............................................................................................ 23
Port List ......................................................................................... 24
SerDes Interface ............................................................................................. 24
Fabric-Side Interface ....................................................................................... 25
DMA-Side Port Descriptions ............................................................................ 36
AXI Target Interface .............................................................................................. 36
AXI Master Interface .............................................................................................. 37
System-to-Card Engine Interface ........................................................................... 38
Card-to-System Engine Interface ........................................................................... 39
Management Interface ........................................................................................... 40
Configuration Register Expansion Interface ........................................................... 43
Appendix A: ACE PCIe Configuration GUI .................................. 45
Appendix B: Verilog Module Description .................................... 71