Achronix Speedster22i PCIe - Manual (Page 52)

UG030, April 26, 2013 52
Field Name Default Values Description Verilog Parameter
reported by all components
comprising the data path from
this Endpoint to the Root
Complex Root Port to determine
whether ASPM L0s entry can be
used with no loss of
performance.” Note that the
amount of buffering refers to user
application buffering. Users
should set this field in accordance
with how long a delay is
acceptable for their application.

000 - Maximum of 64 ns

001 - Maximum of 128 ns

010 - Maximum of 256 ns

011 - Maximum of 512 ns

100 - Maximum of 1 μs

101 - Maximum of 2 μs

110 - Maximum of 4 μs

111 - No limit

Non-Endpoints must
hard wire this field to
000.
L0s Exit
Latency More
than 4us. Less than
64ns, 64ns to
less than
128ns, 128ns
to less than
256ns, 256ns
to less than
512ns, 512ns
to less than
1us, 1us to
less than
2us, 2us-4us,
more than
4us. L0s Exit Latency - Length of time
required to complete transition
from L0s to L0:

000 - Less than 64 ns

001 - 64 ns to less than
128 ns

010 - 128 ns to less than
256 ns

011 - 256 ns to less than
512 ns

100 - 512 ns to less than 1
μs

101 - 1 μs to less than 2 μs

110 - 2 μs-4 μs

111 - More than 4 μs
Exit latencies may be significantly
increased if the PCI Express
reference clocks used by the two
devices in the link are common or
separate.
CFG_CONTROL_PCIE_L
INK_CAP_L0S_EXIT_LA
TENCY
L1 ASPM
Support No No, Yes Active State Power Management
(ASPM) Support

00 - No ASPM support
CFG_CONTROL_PCIE_L
INK_CAP_ASPM_SUPP
ORT