Appendix b: verilog module description – Achronix Speedster22i PCIe User Manual
Page 71
UG030, April 26, 2013
71
Appendix B: Verilog Module
Description
`timescale 1ps/100ps
module ACX_PCIE_WITH_SERDES_WRAP
(///// SERDES PORTS INTERFACE ////
///// REFERENCE CLOCK
//////
pcie_refclk_p
,
pcie_refclk_n
///// SERIAL DATA PINS /////
,
tx_p
// SERIAL TRANSMIT
DIFFERENTIAL PIN (P-SIDE)
,
tx_n
// SERIAL TRANSMIT
DIFFERENTIAL PIN (N-SIDE)
,
rx_p
// SERIAL RECEIVE
DIFFERENTIAL PIN (P-SIDE)
,
rx_n
// SERIAL RECEIVE
DIFFERENTIAL PIN (N-SIDE)
,
i_serdes_sbus_req
,
i_serdes_sbus_data
,
o_serdes_sbus_data
,
o_serdes_sbus_ack
///// FABRIC-SIDE INTERFACE /////
,
perst_n
,
clk_out
///// REGULAR PARALLEL PORTS//
,
i_sbus_clk
,
i_sbus_sw_rst
,
i_sbus_req
,
i_sbus_data
,
o_sbus_data
,
o_sbus_ack
,
bypass_clk
,
bypass_rst_n
,
bypass_tx_valid
,
bypass_tx_ready
,
bypass_tx_almost_full
,
bypass_tx_data
,
bypass_tx_data_valid
,
bypass_tx_sop