IEI Integration NANO-945GSE2 - Manual (Page 7)

NANO-945GSE2
Page vii
5.5.2 Boot Device Priority ...................................................................................... 102
5.6 S ECURITY ............................................................................................................... 102
5.7 C HIPSET ................................................................................................................. 103
5.7.1 Northbridge Chipset Configuration............................................................... 104
5.7.2 Southbridge Configuration ............................................................................ 106
5.8 E XIT ....................................................................................................................... 107
6 SOFTWARE DRIVERS ............................................................................................ 109
6.1 A VAILABLE S OFTWARE D RIVERS .............................................................................110
6.2 S TARTING THE D RIVER P ROGRAM ...........................................................................110
6.3 C HIPSET D RIVER I NSTALLATION ..............................................................................112
6.4 VGA D RIVER I NSTALLATION ...................................................................................116
6.5 LAN D RIVER I NSTALLATION .................................................................................. 120
6.6 A UDIO D RIVER I NSTALLATION ............................................................................... 123
6.6.1 AC’97 Driver Installation .............................................................................. 123
6.7 I NTEL
®
M ATRIX S TORAGE M ANAGER D RIVER I NSTALLATION ................................ 126
6.8 I SMM I NSTALLATION ............................................................................................. 131
A BIOS OPTIONS ........................................................................................................ 138
B TERMINOLOGY...................................................................................................... 142
C DIGITAL I/O INTERFACE..................................................................................... 146
C.1 I NTRODUCTION ...................................................................................................... 147
C.2 DIO C ONNECTOR P INOUTS .................................................................................... 147
C.3 A SSEMBLY L ANGUAGE S AMPLES ........................................................................... 148
C.3.1 Enable the DIO Input Function..................................................................... 148
C.3.2 Enable the DIO Output Function .................................................................. 148
D WATCHDOG TIMER .............................................................................................. 149
E COMPATIBILITY .................................................................................................... 152
E.1 C OMPATIBLE O PERATING S YSTEMS ........................................................................ 153
E.2 C OMPATIBLE P ROCESSORS ..................................................................................... 153
E.3 C OMPATIBLE M EMORY M ODULES .......................................................................... 154
F HAZARDOUS MATERIALS DISCLOSURE........................................................ 155
F.1 H AZARDOUS M ATERIALS D ISCLOSURE T ABLE FOR IPB P RODUCTS C ERTIFIED AS