Rainbow Electronics AT75C220 - Manual (Page 54)

AT75C220
54
cleared during this phase in order to de-assert the
NFIQ line.
6. Finally, the Link Register (R14_FIQ) is restored into
the PC after decrementing it by 4 (e.g., with instruc-
tion SUB PC, LR, #4). This has the effect of
returning from the interrupt to the step previously
executed, of loading the CPSR with the SPSR and
of masking or unmasking the fast interrupt depend-
ing on the state saved in the SPSR.
Note: The F bit in the SPSR is significant. If it is set, it indicates
that the ARM core was just about to mask FIQ interrupts
when the mask instruction was interrupted. Hence, when
the SPSR is restored, the interrupted instruction is com-
pleted (FIQ is masked).
Software Interrupt
Any interrupt source of the AIC can be a software interrupt.
It must be programmed to be edge-triggered in order to set
or clear it by writing to the AIC_ISCR and AIC_ICCR. This
is totally independent of the SWI instruction of the
ARM7TDMI processor.
Spurious Interrupt
A spurious interrupt is a signal of very short duration on one
of the interrupt input lines. A spurious interrupt also arises
when an interrupt is triggered and masked in the same
cycle.
Spurious Interrupt Sequence
A spurious interrupt is handled by the following sequence
of actions.
1. When an interrupt is active, the AIC asserts the
nIRQ (or nFIQ) line and the ARM7TDMI enters IRQ
(or FIQ) mode. At this moment, if the interrupt
source disappears, the nIRQ (or nFIQ) line is de-
asserted but the ARM7TDMI continues with the
interrupt handler.
2. If the IRQ Vector Register (AIC_IVR) is read when
the nIRQ is not asserted, the AIC_IVR is read with
the contents of the Spurious Interrupt Vector
Register.
3. If the FIQ Vector Register (AIC_FVR) is read when
the nFIQ is not asserted, the AIC_FVR is read with
the contents of the Spurious Interrupt Vector
Register.
4. The Spurious ISR must write an End of Interrupt
command as a minimum, however, it is sufficient to
write to the End of Interrupt Command Register
(AIC_EOICR). Until the AIC_EOICR write is
received by the interrupt controller, the nIRQ (or
nFIQ) line is not re-asserted.
5. This causes the ARM7TDMI to jump into the Spuri-
ous Interrupt Routine.
6. During a spurious ISR, the AIC_ISR reads 0.