Rainbow Electronics AT75C220 - Manual (Page 140)

AT75C220
140
WD: Watchdog Timer
The AT75C220 has an internal watchdog timer which can
be used to prevent system lock-up if the software becomes
trapped in a deadlock. In normal operation, the user
reloads the watchdog at regular intervals before the timer
overflow occurs. If an overflow does occur, the watchdog
timer generates one or a combination of the following sig-
nals depending on the parameters in WD_OMR:
• If RSTEN is set, an internal reset is generated
(WD_RESET as shown in Figure 34).
• If IRQEN is set, a pulse is generated on the signal
WDIRQ which is connected to the advanced interrupt
controller
• If EXTEN is set, a low level is driven on the NWDOVF
signal for a duration of eight ACLK cycles.
The watchdog timer has a 16-bit down counter. Bits 12 - 15
of the value loaded when the watchdog is restarted are pro-
grammable using the HPCV parameter in WD_CMR. Four
clock sources are available to the watchdog counter:
ACLK/8, ACLK/32, ACLK/128 or ACLK/1024. The selection
is made using the WDCLKS parameter in WD_CMR. This
provides a programmable time-out period of 1.3 ms to 2.6
seconds with a 24 MHz system clock.
All write accesses are protected by control access keys to
help prevent corruption of the watchdog should an error
condition occur. To update the contents of the mode and
control registers, it is necessary to write the correct bit pat-
tern to the control access key bits at the same time as the
control bits are written (the same write access).
Figure 34. Watchdog Timer Block Diagram
WD User Interface
WD Base Address: 0xFF028000
Offset Register Name Register Description Access Reset Value
0x00 WD_OMR Overflow Mode Register Read/write 0
0x04 WD_CMR Clock Mode Register Read/write 0
0x08 WD_CR Control Register Write-only –
0x0C WD_SR Status Register Read-only 0
Advanced
Peripheral
Bus (APB)
WD_RESET
WDIRQ
ACLK/8
ACLK/32
ACLK/128
ACLK/1024
Control Logic
Clock Select
16-Bit
Programmable
Down Counter
CLK_CNT
Clear
Overflow
NWDOVF