beautypg.com

Sdram refresh, D figure 10. note, Figure 10 – Rainbow Electronics AT75C220 User Manual

Page 26

background image

AT75C220

26

Figure 10. Read Showing a Single Access for a Non-sequential Read to a New Row

Writes can burst continuously until any of the following con-
ditions are achieved:

1.

The following access is a read.

2.

The following access is to a new row.

3.

The following access is non-sequential.

When any of these conditions occur, the write burst is bro-
ken and SDMC goes inactive.

SDRAM Refresh

Table 11 shows the counter values needed for a refresh
rate of 15.625 µs in the SDMC. As can be seen, at clock
speeds of 1 MHz and below it is unfeasible to maintain data
integrity in the SDRAM. Note that in low power modes it is
not a requirement to maintain data in the SDRAM.

BCLK

BA

BTRAN

BWAIT

SDRAM CMD

Addr

sdmc_data

BD

A0

A1

NSEQ

NSEQ

NOP

PRE

NOP

ACT

NOP

READ

NOP

NOP

BANK

ROW

COL0

COL1

D0

D0

INCR

INCR

hburst_h

NOP

Table 11. SDRAM Refresh Rates

Clock Speed (MHz)

Tick (us)

Counter Needed

40

0.25

62.5

8

1.25

12.5

1

10

1.5625

0.025

400

0.0390625

0.0032

3125

0.005