Rainbow Electronics AT75C220 - Manual (Page 34)

AT75C220
34
another buffer can be safely queued. An interrupt is gener-
ated whenever this bit is set.
Frame assembly starts by adding preamble and the start
frame delimiter. Data is taken from the transmit FIFO word-
by-word. If necessary, padding is added to make the frame
length 60 bytes. The CRC is calculated as a 32-bit polyno-
mial. This is inverted and appended to the end of the frame,
making the frame length a minimum of 64 bytes. The CRC
is not appended if the NCRC bit is set in the transmit con-
trol register.
In full duplex mode frames are transmitted immediately.
Back-to-back frames are transmitted at least 96 bit times
apart to guarantee the interframe gap.
In half-duplex mode the transmitter checks carrier sense. If
asserted, it waits for it to de-assert and then starts trans-
mission after the interframe gap of 96 bit times.
If the collision signal is asserted during transmission, the
transmitter will transmit a jam sequence of 32 bits taken
from the data register and then retry transmission after the
backoff time has elapsed. An error is indicated and any fur-
ther attempts aborted if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically
appended using the same mechanism as jam insertion.
Underrun also causes TXER to be asserted.
Receiver Mode
When a packet is received, it is checked for valid preamble,
CRC, alignment, length and address. If all these criteria are
met, the packet is stored successfully in a receive buffer. If
at the end of reception the CRC is bad, then the received
buffer is recovered.
Each received frame including CRC is written to a single
receive buffer.
Receive buffers are word-aligned and are capable of con-
taining 1518 bytes of data (the maximum length of an
Ethernet frame).
The start location for each received frame is stored in
memory in a list of receive buffer descriptors at a location
pointed to by the receive buffer queue pointer register.
Each entry in the list consists of two words. The first word is
the address of the received buffer; the second is the
receive status. Table 14 defines an entry in the received
buffer descriptor list.
To receive frames, the buffer queue must be initialized by
writing an appropriate address to bits [31:2] in the first word
of each list entry. Bit zero must be written with zero. After a
frame is received, bit zero becomes set and the second
word indicates what caused the frame to be copied to
memory.
The start location of the received buffer descriptor list
should be written to the received buffer queue pointer reg-
ister before receive is enabled (by setting the receive
enable bit in the network control register). As soon as the
received block starts writing received frame data to the
receive FIFO, the received buffer manager reads the first
receive buffer location pointed to by the received buffer
queue pointer register. If the filter block is active, the frame
should be copied to memory; the receive data DMA opera-
tion starts writing data into the receive buffer. If an error
occurs, the buffer is recovered. If the frame is received
without error, the queue entry is updated. The buffer
pointer is rewritten to memory with its low-order bit set to
indicate successful frame reception and a used buffer. The
next word is written with the length of the frame and how
the destination address was recognized.
The next receive buffer location is then read from the fol-
lowing word or, if the current buffer pointer had its wrap bit
set, the beginning of the table. The maximum number of
buffer pointers before a wrap bit is seen is 1024. If a wrap
bit is not seen by then, a wrap bit is assumed in that entry.
The received buffer queue pointer register must be written
with zero in its lower-order bit positions to enable the wrap
function to work correctly.
If bit zero is set when the receive buffer manager reads the
location of the receive buffer, then the buffer has already
been used and cannot be used again until software has
processed the frame and cleared bit zero. In this case, the
DMA block will set the buffer’s unavailable bit in the
received status register and trigger an interrupt. The frame
will be discarded and the queue entry will be reread on
reception of the next frame to see if the buffer is now avail-
able. Each discarded frame increments a statistics register
that is cleared on being read.
When there is network congestion, it is possible for the
MAC to be programmed to apply backpressure. This is
when half-duplex mode collisions are forced on all received
frames by transmitting 64 bits of data (a default pattern).
Reading the received buffer queue register returns the
location of the queue entry currently being accessed. The
queue wraps around to the start after either 1024 entries
(i.e., 2048 words) or when the wrap bit is found to be set in
bit 1 of the first word of an entry.