Rainbow Electronics AT75C220 - Manual (Page 52)

AT75C220
52
Priority Controller
The NIRQ line is controlled by an 8-level priority encoder.
Each source has a programmable priority level of 7 to 0.
Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt
at a time, the interrupt with the highest priority is serviced
first. If both interrupts have equal priority, the interrupt with
the lowest interrupt source number is serviced first.
The current priority level is defined as the priority level of
the current interrupt at the time the register AIC_IVR is
read (the interrupt which will be serviced). In the case when
a higher priority unmasked interrupt occurs while an inter-
rupt already exists, there are two possible outcomes
depending on whether the AIC_IVR has been read.
1. If the NIRQ line has been asserted but the AIC_IVR
has not been read, then the processor will read the
new higher priority interrupt handler number in the
AIC_IVR register and the current interrupt level is
updated.
2. If the processor has already read the AIC_IVR, then
the NIRQ line is reasserted. When the processor
has authorized nested interrupts to occur and reads
the AIC_IVR again, it reads the new, higher priority
interrupt handler address. At the same time the cur-
rent priority value is pushed onto a first-in last-out
stack and the current priority is updated to the
higher priority.
W h e n t h e E n d o f I n t e r r u p t C o m m a n d R e g i s t e r
(AIC_EOICR) is written, the current interrupt level is
updated with the current interrupt level from the stack (if
any). Hence, at the end of a higher priority interrupt, the
AIC returns to the previous state corresponding to the pre-
ceding lower priority interrupt which had been interrupted.
Interrupt Handling
The interrupt handler must read the AIC_IVR as soon as
possible. This deasserts the NIRQ request to the processor
and clears the interrupt in case it is programmed to be
edge-triggered. This permits the AIC to assert the NIRQ
line again when a higher priority unmasked interrupt
occurs.
At the end of the interrupt service routine, the End of Inter-
rupt Command Register (AIC_EOICR) must be written.
This allows pending interrupts to be serviced.
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or
disabled using the command registers AIC_IECR and
AIC_IDCR. The interrupt mask can be read in the read only
register AIC_IMR. A disabled interrupt does not affect the
servicing of other interrupts.
Interrupt Clearing and Setting
All interrupt sources which are programmed to be edge-
triggered (including FIQ) can be individually set or cleared
by respectively writing to the registers AIC_ISCR and
AIC_ICCR. This function of the interrupt controller is avail-
able for auto-test or software debug purposes.
Standard Interrupt Sequence
It is assumed that:
• The advanced interrupt controller has been
programmed, AIC_SVR registers are loaded with
corresponding interrupt service routine addresses and
interrupts are enabled.
When NIRQ is asserted and if the bit I of CPSR is 0, the
sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value
of the Program Counter is loaded in the IRQ link
register (R14_IRQ) and the Program Counter (R15)
is loaded with 0x18. In the following cycle during
fetch at address 0x1C, the ARM core adjusts
R14_IRQ, decrementing it by 4.
2. The ARM core enters IRQ mode if it is not already.
3. When the instruction at 0x18 is executed, the Pro-
gram Counter is loaded with the value read in the
AIC_IVR. Reading the AIC_IVR has the following
effects:
Sets the current interrupt to be the pending one with
the highest priority. The current level is the priority level
of the current interrupt.
De-assserts the nIRQ line on the processor (even if
vectoring is not used, AIC_IVR must be read in order to
de-assert nIRQ).
Automatically clears the interrupt if it has been pro-
grammed to be edge-triggered.
Pushes the current level on to the stack.
Returns the AIC_SVR corresponding to the current
interrupt.
14 UARTB USART B Interrupt
15 PIOB PIO B Interrupt
16 - 31 Reserved
Table 17. Interrupt Sources (Continued)
Interrupt Source Interrupt Name Interrupt Description