Rainbow Electronics AT75C220 - Manual (Page 53)

AT75C220
53
4. The previous step establishes a connection to the
corresponding ISR. This begins by saving the link
register (R14_IRQ) and the SPSR (SPSR_IRQ).
Note that the link register must be decrermented by
4 when it is saved if it is to be restored directly into
the Program Counter at the end of the interrupt.
5. Further interrupts can then be unmasked by clear-
ing the I bit in the CPSR, allowing re-assertion of
the NIRQ to be taken into account by the core. This
can occur if an interrupt with a higher priority than
the current one occurs.
6. The interrupt handler then proceeds as required,
saving the registers which are used and restoring
them at the end. During this phase, an interrupt of
priority higher than the current level will restart the
sequence from step 1. Note that if the interrupt is
programmed to be level-sensitive, the source of the
interrupt must be cleared during this phase.
7. The I bit in the CPSR must be set in order to mask
interrupts before exiting to ensure that the interrupt
is completed in an orderly manner.
8. The service routine should then connect to the com-
mon exit routine.
9. The End Of Interrupt Command Register
(AIC_EOICR) must be written in order to indicate to
the AIC that the current interrupt is finished. This
causes the current level to be popped from the
stack, restoring the previous current level if one
exists. If another interrupt with lower or equal prior-
ity than the old current level is pending, the nIRQ
line is re-asserted but the interrupt sequence does
not immediately start because the I bit is set in the
core.
10. The SPSR (SPSR_IRQ) is restored. Finally, the
saved value of the Link Register is restored directly
into the PC. This has the effect of returning from the
interrupt to the step previously executed, of loading
the CPSR with the stored SPSR and of masking or
unmasking the interrupts depending on the state
saved in the SPSR (the previous state of the ARM
core).
Note: The I bit in the SPSR is significant. If it is set, it indicates
that the ARM core was just about to mask IRQ interrupts
when the mask instruction was interrupted. Hence, when
the SPSR is restored, the mask instruction is completed
(IRQ is masked).
Fast Interrupt
The external FIQ line is the only source which can raise a
fast interrupt request to the processor. Therefore it has no
priority controller. It can be programmed to be positive- or
negative-edge triggered or high- or low-level sensitive in
the AIC_SMR0 register.
The fast interrupt handler address can be stored in the
AIC_SVR0 register. The value written into this register is
available by reading the AIC_FVR register when an FIQ
interrupt is raised. By storing the following instruction at
address 0x0000001C, the processor will load the program
counter with the interrupt handler address stored in the
AIC_FVR register.
LDR PC, [PC, #-&F20]
Alternatively, the interrupt handler can be stored starting
from address 0x0000001C as described in the ARM7TDMI
datasheet.
Fast Interrupt Sequence
It is assumed that:
• The advanced interrupt controller has been
programmed, AIC_SVR[0] is loaded with the fast
interrupt service routine address and the fast interrupt is
enabled.
• Nested fast interrupts are not needed by the user.
When NFIQ is asserted, if the bit F of CPSR is 0, the
sequence is:
1. The CPSR is stored in SPSR_fiq, the current value
of the Program Counter is loaded in the FIQ link
register (R14_FIQ) and the Program Counter (R15)
is loaded with 0x1C. In the following cycle, during
fetch at address 0x20, the ARM core adjusts
R14_FIQ, decrementing it by 4.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is
executed, the Program Counter is loaded with the
value read in AIC_FVR. Reading the AIC_FVR has
the effect of clearing the fast interrupt (source 0
connected to the FIQ line) if it has been pro-
grammed to be edge-triggered. In this case only, it
de-asserts the nFIQ line on the processor.
4. The previous step establishes a connection to the
corresponding interrupt service routine. It is not
necessary to save the Link Register (R14_FIQ) and
the SPSR (SPSR_FIQ) if nested fast interrupts are
not needed.
5. The interrupt handler can then proceed as required.
It is not necessary to save registers R8 to R13
because FIQ mode has its own dedicated registers
and the user R8 to R13 are banked. The other reg-
isters, R0 to R7, must be saved before being used
and restored at the end (before the next step). Note
that if the fast interrupt is programmed to be level-
sensitive, the source of the interrupt must be