Rainbow Electronics AT75C220 - Manual (Page 17)

AT75C220
17
For a 32-bit bus:
• The signal NWE0 is used as the write enable signal for
byte 0.
• The signal NWE1 is used as the write enable signal for
byte 1.
• The signal NWE2 is used as the write enable signal for
byte 2.
• The signal NWE3 is used as the write enable signal for
byte 3.
• The signal NSOE enables memory reads to all memory
blocks.
For a 16-bit bus:
• The signal NWE0 is used as the write enable signal for
byte 0.
• The signal NWE1 is used as the write enable signal for
byte 1.
• The signal NSOE enables memory reads to all memory
blocks.
Byte-select mode can be used to connect one 32-bit device
or two 16-bit devices in a 32-bit memory page or one 16-bit
device in a 16-bit memory page.
For a 32-bit bus:
• The signal NWE0 is used to select byte 0 for read and
write operations.
• The signal NWE1 is used to select byte 1 for read and
write operations.
• The signal NWE2 is used to select byte 2 for read and
write operations.
• The signal NWE3 is used to select byte 3 for read and
write operations.
• The signal NWR is used as the write enable signal for
the memory block.
• The signal NSOE enables memory reads to the memory
block.
For a 16-bit bus:
• The signal NWE0 is used to select byte 0 for read and
write operations.
• The signal NWE1 is used to select byte 1 for read and
write operations.
• The signal NWR is used as the write enable signal for
the memory block.
• The signal NSOE enables memory reads to the memory
block.
During boot, the number of external devices (number of
active chip selects) and their configurations must be pro-
grammed as required. The chip select addresses that are
programmed take effect immediately. Wait states also take
effect immediately when they are programmed to optimize
boot program execution.
Read Protocols
The SMC provides two alternative protocols for external
memory read access: standard and early read. The differ-
ence between the two protocols lies in the timing of the
NSOE (read cycle) waveform.
The protocol is selected by the DRP field in the Memory
Control Register (SMC_MCR) and is valid for all memory
devices. Standard read protocol is the default protocol after
reset.
• Standard Read Protocol
Standard read protocol implements a read cycle in which
NSOE and the write strobes are similar. Both are active
during the second half of the clock cycle. The first half of
the clock cycle allows time to ensure completion of the pre-
vious access, as well as the output of address and NCE
before the read cycle begins.
During a standard read protocol external memory access,
NCE is set low and ADDR is valid at the beginning of the
access, whereas NSOE goes low only in the second half of
the master clock cycle to avoid bus conflict. The write
strobes are the same in both protocols. The write strobes
always go low in the second half of the master clock cycle.
• Early Read Protocol
Early read protocol provides more time for a read access
from the memory by asserting NSOE at the beginning of
the clock cycle. In the case of successive read cycles in the
same memory, NSOE remains active continuously. Since a
read cycle normally limits the speed of operation of the
external memory system, early read protocol allows a
faster clock frequency to be used. However, an extra wait
state is required in some cases to avoid contention on the
external bus.
In early read protocol, an early read wait state is automati-
cally inserted when an external write cycle is followed by a
read cycle to allow time for the write cycle to end before the
subsequent read cycle begins. This wait state is generated
in addition to any other programmed wait states (i.e., data
float wait). No wait state is added when a read cycle is fol-
lowed by a write cycle, between consecutive accesses of
the same type or between external and internal memory
accesses. Early read wait states affect the external bus
only. They do not affect internal bus timing.
Write Protocol
During a write cycle, the data becomes valid after the fall-
ing edge of the write strobe signal and remains valid after
the rising edge of the write strobe. The external write strobe
waveform on the appropriate write strobe pin is used to
control the output data timing to guarantee this operation.
Thus, it is necessary to avoid excessive loading of the write
strobe pins, which could delay the write signal too long and
cause a contention with a subsequent read cycle in stan-
dard protocol. In early read protocol, the data can remain