Rainbow Electronics AT75C220 - Manual (Page 12)

AT75C220
12
AT75C220 Mode Controller
The ARM configures the mode of the AT75C220 by means
of the SIAP-E mode controller. The SIAP-E mode controller is a memory-mapped periph-
eral that sits on the APB bus.
Register Map
Base Address: 0xFF000000
Note: 1. If the PKG flag is set, the reset value is 0x00010220 since the AT75C220 is bonded in large bond-out mode.
SIAP-E Mode Register
Register Name: SIAP_MD
Access: Read/write
Reset Value: 0x00B0342
• RM: Remap
On reset being released this flag is set to the value of NDSRA/BOOTN. When RM is active low the Boot ROM is
mapped to location 0x00000000. Subsequently, this flag can be set high by software so that the ROM mapping is dis-
abled and another memory controller region (e.g. FLASH) is mapped to location 0x00000000.
• RA: OAKA Reset
This flag resets to active low so that the OAKA is held in reset. The OAKA is be released from reset by asserting this
flag high.
• IA: Inhibit OAKA Clock
This flag resets to active low so that the OAKA clock is enabled. The OAKA clock is be inhibited by asserting this flag
high.
• LP: Low Power Mode
On reset this field is high. When written high the PLL is disabled and the ARM and OAK cores and logic are clocked at
the low power clock frequency. Note, in this mode the ARM and OAK are clocked at the same frequency determined by
the LPCS field. When LP is written low the PLL is enabled and once it has locked the clock is switched over to the nor-
mal operating frequency.
Table 5. AT75C220 Register Map
Register Address Register Name Description Access Reset Value
0x0 SIAP_MD SIAP-E Mode Register Read/write 0x00B0340
0x4 SIAP_ID SIAP-E ID Register Read-only 0x0000220 (1)
0x8 SIAP_RST SIAP-E Reset Status
Register Read/write 0x0000001
0xC SIAP_CLKF SIAP-E Clock Status
Register Read-only 0x0000001
31 30 29 28 27 26 25 24
– – JCIDBG OUTDIV INDIV
23 22 21 20 19 18 17 16
ICP IPOLTST
15 14 13 12 11 10 9 8
– CRA – DBA SW2 SW1 LPCS
7 6 5 4 3 2 1 0
SA LP – – IA – RA RM