beautypg.com

Ds1862 xfp laser control and digital diagnostic ic, C operation using packet error checking – Rainbow Electronics DS1862 User Manual

Page 39

background image

DS1862

XFP Laser Control and Digital Diagnostic IC

____________________________________________________________________

39

I

2

C Operation using

Packet Error Checking

Read Operation with

Packet Error Checking

Packet error checking during reads is supported by the
DS1862. Information is transferred form the DS1862 in
much the same way as conventional I

2

C protocol, how-

ever, an extra CRC field is added and checked. The
still begins by sending the device address (A0h for
DS1862), then the index pointer to the memory address
of interest. The next byte transferred, however will be
the value of the intended number of bytes to be read.
The calculation of the CRC-8 includes and requires the
explicit starting memory address to be included as the
second transferred byte (dummy write byte). Next, the
slave transfers the data back as the master acknowl-
edges. Only 1 to 128 bytes can be sequentially read
during one transmission while using PEC. After the
master reads the intended number of bytes, the CRC-8
value is transmitted by the DS1862. The master ends

the communication with a NACK and a STOP. See
Figure 16 for a graphical representation. The CRC-8 is
calculated starting with the MSB of the memory
address pointer, number of bytes to read, and the read
data. The master can then verify the CRC-8 value and
reject the read data if the CRC-8 value does not corre-
spond to the received CRC value. The CRC-8 must be
calculated by using the following polynomial for both
reads and writes:

C(x) = X

8

+X

2

+ X + 1

Write Operation with

Packet Error Checking

Packet error checking during writes is also supported
by the DS1862. Information is written to the DS1862 in
much the same way as conventional I

2

C protocol, how-

ever, an extra CRC field is added and checked. The
master still begins by sending the device address, then
the index pointer to the memory address of interest.
The next byte however, will be the value of the intended
number of bytes to be written. The calculation of the

X

X

X

X

X

X

X

X

1

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

COMMUNICATIONS KEY

WRITE A SINGLE BYTE

WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION

READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER

READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER

8-BITS ADDRESS OR DATA

WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA

THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.

SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA

START

ACK

NOT
ACK

S

S

S

S

S

A

A

A

A

A

A

A

P

A

A

SR

SR

A

A

A

P

N

P

N

P

A

A

DATA

DATA

DATA

DATA

DATA

DATA

DATA

MEMORY ADDRESS

MEMORY ADDRESS

MEMORY ADDRESS

MEMORY ADDRESS

DATA

A

A

A

P

N

SR

STOP

REPEATED
START

NOTE:
ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.

Figure 15. I

2

C Communications Examples