Rainbow Electronics DS1862 - Manual (Page 31)

DS1862
XFP Laser Control and Digital Diagnostic IC
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Bit 0: DATA_NOT_READY. Bit is high until DS1862 has achieved power-up. Bit goes low, signaling that monitor
channel data is ready to be read.
Bit 1: RX-LOS. Indicates optical loss of the signal and is updated within t LOS-ON .
Bit 2: Interrupt. Indicates the state of the INTERRUPT pin and is updated within t
INIT ON
.
Bit 3: Soft P-DOWN/RST. R/W bit that places the DS1862 in power-down mode. Toggle to reset.
Bit 4: P-DOWN/RST. Indicates the digital state of the P-DOWN/RST pin and is updated within t PDR-ON .
Bit 5: MOD_NR State. Indicates the state of MOD_NR pin and is updated within t PDR-ON .
Bit 6: Soft TX-D. R/W bit that disables (shuts down) I BIASSET and I MODSET .
Bit 7: TX-D. Indicates the digital state of the TX-D pin and is updated within t OFF .
6Fh
• 6Fh GCS0 ........................< R-all / W-all > These are nonlatched flags, indicating the real-time
digital state of a corresponding signal.
Bit 0: Reserved.
Bit 1: Reserved.
Bit 2: Reserved.
Bit 3: RX_CDR not locked. Indicates LOL in Rx path CDR.
Bit 4: RX_NR state. Indicates a NOT READY condition in the Rx path.
Bit 5: Reserved.
Bit 6: TX-FAULT State. Indicates a laser safety fault condition.
Bit 7: TX-NR State. Indicates a NOT READY condition on the Tx path.
74h
• POA..................................< R-all / W-all ><00> A high on bit 7 indicates that V
CC3 is below the
Power-on analog trip point, POA.
76h
• PEC Enable......................< R-all / W-all ><00> Bit 0 is used to enable PEC. A value of 1 enables
PEC.
77h
→ 7Ah
• Host PW Change .............< R-never / W-Host ><00> This is the 32-bit location that
the DS1862 uses to compare with the PWE to grant host password access.
7Bh
→ 7Eh
• PWE .................................< R-never / W-all ><00> This is the 32-bit location that is used to enter the
host and module password to gain acess to the DS1862.
7Fh
• Table Select .....................< R-all / W-all ><01> This is the 8-bit register that controls which section
of upper memory (table) is being adressed by I 2 C. A value of 00h and 01h results in
adressing Table 01h. Values above 05h are accepted, but do not correspond to any
physical memory.
Table 01h
80h
→ DBh
• User EE ............................< R-all / W-Module ><00>
DCh
• V
CC2/3 _Sel ....................... < R-all / W-Module ><00> Bit 0 of this register controls
whether V
CC2
or V
CC3
is internally measured by the V
CC2/3
monitor channel. A ‘1’
selects V
CC2
to be measured.