Rainbow Electronics DS1862 - Manual (Page 24)

DS1862
XFP Laser Control and Digital Diagnostic IC
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During an asserted period of P-DOWN/RST (DS1862 in
power-down), and V
CC3 is cycled, the DS1862 remains
in power-down mode upon power-up. While in power-
down mode the
INTERRUPT pin does not assert. Once
V
CC3
has returned, the reset done flag asserts after the
interrupt assert delay, t INIT ON .
Reset Functionality
Besides powering down the DS1862, the P-DOWN/RST
pin also functions to reset the DS1862. After a high-
going pulse of time t
RESET
, several events occur within
the DS1862. First, MODSET and BIASSET currents shut
down and are then reinstated. Second, between the ris-
ing edge of the reset pulse and the assertion of the
reset-done flag (t
INIT ), the low TX-P flag is ignored and
does not cause FETG to trip. After time t INIT, the low
TX-P flag becomes functional. Also, at this time, the
reset-done flag is asserted, causing an interrupt to be
generated. If there are no faults before t
INIT , then no
interrupts are asserted on the INTERRUPT pin.
If V
CC3
is powered up while P-DOWN/RST is high, then
the reset-done flag must be cleared twice. The first time
the reset-done flag is generated by V
CC3 powering up,
the second time reset-done is generated by a falling
edge on P-DOWN/RST. If V
CC3 is continuously pow-
ered while P-DOWN/RST is low then only one reset-
done flag needs to be cleared. See the timing
diagrams for graphical detail.
DS1862 Memory Map
Memory Organization
The DS1862 features six separate memory tables that
are internally organized into four byte rows. The Lower
Memory is addressed from 00h to 7Fh and contains
alarm and warning thresholds, flags, masks, several
control registers, password entry area (PE), and the
Table Select byte. Table 01h primarily contains user
EEPROM as well as several control bytes for various
functions. Table 02h is strictly user EEPROM that is pro-
tected by a host password. Table 03h is strictly used
for controlling the extinction ratio with an LUT. Table
04h is a multifunction space that contains internal cali-
bration values for monitored channels, LUT index point-
ers, and miscellaneous control bytes. Table 05h is
factory programmed and stores SCALE values for use
with suggested external temperature sensors. Also, one
byte in Table 05h controls the THRSET voltage source
and is completely accessible without any password
protection. See the Memory section for a more com-
plete detail of each byte’s function, as well as Table 11
for read/write permissions for each Byte. Many non-
volatile memory locations (listed within the Detailed
Register Description section) are actually SRAM-
Shadowed EEPROM, which are controlled by the SEEB
bit in Table 4, Byte B2h.
The DS1862 incorporates SRAM-shadowed EEPROM
memory locations for key memory addresses that may
be rewritten many times. By default the Shadowed
EEPROM Bit, SEEB, is not set and these locations act
as ordinary EEPROM. By setting SEEB, these loca-
tions begin to function like SRAM cells, which allow an
infinite number of write cycles without concern of wear-
ing out the EEPROM. This also eliminates the require-
ment for the EEPROM write time, t
WR
. Because
changes made with SEEB enabled do not affect the
EEPROM, these changes are not retained through
power cycles. The power-up value is the last value writ-
ten with SEEB disabled. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during
normal operation helping to reduce the number of times
EEPROM is written. The Memory Map description indi-
cates which locations are shadowed-EEPROM.