Rainbow Electronics DS1862 - Manual (Page 36)

DS1862
XFP Laser Control and Digital Diagnostic IC
36 ____________________________________________________________________
Security/Password Protection
The DS1862 features two separate and independent
32-bit passwords for important memory locations. The
host password and the module password allow their
own allocated memory locations to be locked to pre-
vent write and/or read access. To enhance the security
of the DS1862, the Password Entry and Setting bytes
can never be read.
To gain access to host-protected or module-protected
memory locations, the correct 32-bit value must be
entered in to the password entry bytes (PWE) in either a
single four-byte write, or four single-byte writes. To repro-
gram either password, simply enter the appropriate cur-
rent password to gain memory access, write the new Host
or Module PW with one four-byte write, and finally reenter
the new password into the PWE to regain memory access.
Power-Up Sequence
The DS1862 does require a particular power-up
sequence to ensure proper functionality. V
CC3 should
always be applied first or at the same time as V CC2 . If
this power-up sequence is not followed, then current can
be sourced out of V
CC2 as if it was connected to V CC3
with a resistor internal to the DS1862. If V CC2 is not used
then it should be externally connected to V
CC3
.
Signal Conditioners—
EN1 and EN2 and VTHRES
Signal Conditioners—EN1 and EN2
The EN1 and EN2 output pins are controlled by the bits
at address 01h, bits 2 and 1. The logic state of the pins
is directly analogous to the logical state of the register.
EN1 and EN2 automatically change to a high and low
state, respectively, during power-down mode as
described in the Power-Down Functionality section.
Signal Conditioners—VTHRES
A programmable voltage source, THRSET is also pro-
vided for use with signal conditioners. This source is
programmable from 0 to 1V in 256 increments.
I 2 C and Packet Error
Checking (PEC) Information
The DS1862 supports I 2 C data transfers as well as data
transfers with PEC. The slave address is unalterable
and is set to A0h. The DS1862, however, does have an
additional dedicated pin, MOD-DESEL, which acts as
an active-low chip select to enable communication. See
the I
2 C Serial Interface and the I 2 C Operation Using
Packet Error Checking sections for details.
Precision SCALE Register
Settings for AUX2MON
The DS1862 features a factory-trimmed SCALE value
for use with DS60 or LM50 temperature sensors. If
external temperature measurement on AUX2MON is
used with one of these two sensors, the 16-bit SCALE
value can be read from Table 05h and written into the
SCALE register in Table 04h, Byte 9Ch and 9Dh. This
option allows for the most precise setting for SCALE
without requiring additional trimming. Since the SCALE
register value is precisely trimmed at the factory, the
OFFSET register will always be a non-unique value and
can simply be written into are OFFSET register. For the
DS60, the value of EF0Ah in OFFSET completes the
internal calibration. For the LM50, the value of F380h in
OFFSET completes the internal calibration.
I 2 C Serial Interface
I 2 C Definitions
The following terminology is commonly used to describe
I
2 C data transfers.
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See Figure 14 for
applicable timing.
Stop condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a stop condition. See Figure 14 for applicable timing.
Repeated start condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed start condition is issued identically to a normal start
condition. See Figure 14 for applicable timing.