Ds1862 xfp laser control and digital diagnostic ic – Rainbow Electronics DS1862 User Manual
Page 27
DS1862
XFP Laser Control and Digital Diagnostic IC
____________________________________________________________________
27
EXPANDED BYTES (CONTINUED)
Bit7
Bit6*
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0**
BYTE
(hex)
BYTE/WORD
NAME
bit
15
bit
14
bit
13
bit
12
bit
11
bit
10
bit
9
bit
8
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
57
<1>
L-HI-V
CC5
-W L-LO-V
CC5
-W L-HI-V
CC3
-W L-LO-V
CC3
-W L-HI-V
CC2
-W L-LO-V
CC2
-W L-HI-V
EE5
-W L-LO-V
EE5
-W
58
<1>
HI-TEMP-AL
MASK
LO-TEMP-AL
MASK
Reserved
Reserved
HI-BIAS-AL
MASK
LO-BIAS-AL
MASK
HI-TX-P-AL
MASK
LO-TX-P-AL
MASK
59
<1>
HI-RX-P-AL
MASK
LO-RX-P-AL
MASK
HI-AUX1-AL
MASK
LO-AUX1-AL
MASK
HI-AUX2-AL
MASK
LO-AUX2-AL
MASK
Reserved
Reserved
5A
<1>
HI-TEMP-W
MASK
LO-TEMP-W
MASK
Reserved
Reserved
HI-BIAS-W
MASK
LO-BIAS-W
MASK
HI-TX-P-W
MASK
LO-TX-P-W
MASK
5B
<1>
HI-RX-P-W
MASK
LO-RX-P-W
MASK
HI-AUX1-W
MASK
LO-AUX1-W
MASK
HI-AUX2-W
MASK
LO-AUX2-W
MASK
Reserved
Reserved
5C
<1>
TX-NR MASK TX-F MASK
TX-CDR-NL
MASK
RX-NR MASK
RX-LOL
MASK
RX-CDR-NL
MASK
MOD-NR
MASK
RESET-
DONE MASK
5D
<1>
APD-SUP-F
MASK
TEC-F MASK
WAVE-NL
MASK
Reserved
Reserved
Reserved
Reserved
Reserved
5E
<1>
HI-V
CC5
-AL
MASK
LO-V
CC5
-AL
MASK
HI-V
CC3
-AL
MASK
LO-V
CC3
-AL
MASK
HI-V
CC2
-AL
MASK
LO-V
CC2
-AL
MASK
HI-V
EE5
-AL
MASK
LO-V
EE5
-AL
MASK
5F
<1>
HI-V
CC5
-W
MASK
LO-V
CC5
-W
MASK
HI-V
CC3
-W
MASK
LO-V
CC3
-W
MASK
HI-V
CC2
-W
MASK
LO-V
CC2
-W
MASK
HI-V
EE5
-W
MASK
LO-V
EE5
-W
MASK
6E
<1>
TX-D
SOFT TX-D
MOD-NR
P-DOWN/RST
SOFT
P-DOWN
INTERRUPT
RX-LOS
DATA-NR
6F
<1>
TX-NR
TX-F
TX-CDR-NL
RX-NR
RX-CDR-NL
Reserved
Reserved
Reserved
74
POA <1>
POA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
77
Host PW
<6>
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
78
Host PW
<6>
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
79
Host PW
<6>
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
7A
Host PW
<6>
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
7B
PWE
<6>
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
7C
PWE
<6>
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
7D
PWE
<6>
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
7E
PWE
<6>
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
7F
Table Select
<1>
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
*Bit 6 and Bit 3 of Byte 6Eh are masked by Bit 6 and Bit 5 of Byte DDh in Table 01h, respectively.
**Bit 0 of Address 01h can be written only if Bit 0 of Byte DDh in Table 01h is set.