Intel SE7525GP2 - Manual (Page 68)

Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0 68
3.8 Clock Generation and Distribution
All buses on the server board operate using synchronous clocks. Clock synthesizer/driver
circuitry on the server board generates clock frequencies and voltage levels as required,
including the following:
• 200MHz differential Clock at 0.7 V logic levels. For Processor 0, Processor 1, Debug
Port and MCH.
• 100 MHz differential Clock at 0.7 V logic levels on CK409B. For DB800 clock buffer.
• 100 MHz differential Clock at 0.7 V logic levels on DB800. For PCI Express Device is
MCH. And for SATA is Intel 6300ESB.
• 66 MHz at 3.3 V logic levels: For MCH and Intel 6300ESB
• 48 MHz at 3.3V logic levels: For Intel 6300ESB and SIO.
• 33 MHz at 3.3V logic levels: For Intel 6300ESB, Video, BMC and SIO.
• 14.318 MHz at 2.5 V logic levels: For Intel 6300ESB and Video.
• 10 Mhz at 5V logic levels: For mini BMC.
3.8.1 Real Time Clock
The real time clock is specified to operate within the following criteria and environmental
conditions:
RTC Accuracy: 1 minute per month = 2 seconds per day
Environmental Conditions:
Temperature 10 ~ 35 C
Humidity 20 ~80% (non-condensing)