Intel SE7525GP2 - Manual (Page 48)

Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0 48
Table 10: Interrupt Definitions
ISA Interrupt Description
INTR Processor interrupt.
NMI NMI to processor.
IRQ0 System timer
IRQ1 Keyboard interrupt.
IRQ2 Slave PIC
IRQ3 Serial port 1 or 2 interrupt from SUPER IO device, user-configurable.
IRQ4 Serial port 1 or 2 interrupt from SUPER IO device, user-configurable.
IRQ5 Parallel Port / Generic
IRQ6 Floppy disk.
IRQ7 Generic
IRQ8_L
Active low RTC interrupt.
IRQ9 SCI*
IRQ10 Generic
IRQ11 Generic
IRQ12 Mouse interrupt.
IRQ13 Floating point processor.
IRQ14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15 Secondary IDE Cable
SMI* System Management Interrupt. General purpose indicator sourced by the 6300ESB to the
processors.
3.6.3.4 Serialized IRQ Support
The Intel Server Boards SE7320SP2 and SE7525GP2 support a serialized interrupt delivery
mechanism. Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17
IRQ / data channels, and a stop frame. Any slave device in the quiet mode may initiate the start
frame. While in the continuous mode, the start frame is initiated by the host controller.
3.6.3.5 IRQ Scan for PCIIRQ
The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with
the standard implementation using the minimum 17 sampling channels. The Intel Server Boards
SE7320SP2 and SE7525GP2 have an external PCI interrupt serializer for PCIIRQ scan
mechanism of Intel 6300ESB I/O Controller to support 16 PCIIRQs.