Intel SE7525GP2 - Manual (Page 29)

Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Revision 2.0 29
Table 3: Processor Support Matrix
Processor Family FSB Frequency Frequency Support
Intel® Xeon™ 533 MHz 2.8 GHz No
Intel® Xeon™ 533 MHz 3.06 GHz No
Intel® Xeon™ 533 MHz 3.2 GHz No
Intel® Xeon™ 800MHz 2.8 GHz Yes
Intel® Xeon™ 800MHz 3.0 GHz Yes
Intel® Xeon™ 800MHz 3.2 GHz Yes
Intel® Xeon™ 800MHz 3.4 GHz Yes
Intel® Xeon™ 800MHz 3.6 GHz Yes
3.1.6.1 Processor Mis-population Detection
The processors must be populated in the correct order for the processor Front Side Bus to be
correctly terminated. CPU socket 1 must be populated before CPU socket 2. Server board logic
will prevent the system from powering up if a single processor is present but it is not in the
correct socket. This protects the logic against voltage swings or unreliable operation that could
occur on an incorrectly terminated Front Side Bus.
If processor mis-population is detected when using the standard on-board platform
instrumentation, the mBMC will log an error against processor 1 to the System Event Log and
the server board hardware will illuminate both processor error LEDs.
3.1.6.2 Mixed Processor Steppings
For optimum system performance, only identical processors should be installed in a system.
Processor steppings within a common processor family can be mixed in a system provided that
there is no more than a one stepping difference between them. If the installed processors are
more than one stepping apart, an error is reported. Acceptable mixed steppings are not
reported as errors by the BIOS.
3.1.6.3 Mixed Processor Models
Processor models cannot be mixed in a system. If this condition is detected, an error (8196) is
logged in the SEL.
3.1.6.4 Mixed Processor Families
Processor families cannot be mixed in a system. If this condition is detected, an error (8194) is
logged in the SEL.
3.1.6.5 Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error (8192) will be logged in the SEL.
The size of all cache levels must match between all installed processors. Mixed cache
processors are not supported.