Intel SE7525GP2 - Manual (Page 120)

Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Platform Management
Revision 2.0 120
5.3.1.1 Power-up Sequence
When turning on the system power in response to one of the event occurrences listed in
Table 51 below, the mBMC executes the following procedure:
1. The mBMC asserts Power On and waits for the power subsystem to assert Power
Good. The system is held in reset.
2. The mBMC sends a Set ACPI Power State command, indicating an S0 state to all
management controllers whose SDR management device records indicate that they
should receive the notification.
3. The mBMC initializes all sensors to their Power On initialization state. The Init Agent is
run.
4. The mBMC attempts to boot the system by running the FRB algorithm.
5.3.1.2 Power-down Sequence
To power down the system, the mBMC effectively performs the sequence of power-up steps in
reverse order. This operation can be initiated by one of the event occurrences listed in Table 51
and proceeds as follows:
1. The mBMC asserts system reset (de-asserts Power Good).
2. If enabled, the mBMC sends a Set ACPI Power State command, indicating an S0 state
to all management controllers whose SDR management device records indicate that
they should receive the notification.
3. The mBMC de-asserts the Power On signal.
4. The power subsystem turns off system power upon de-assertion of the Power On
signal.
5.3.1.3 Power Control Sources
The sources listed in the following table can initiate power-up and/or power-down activity.
Table 51: Power Control Initiators
# Source
External Signal Name or
Internal Subsystem
Capabilities
1 Power Button FP Power button Turns power ON or OFF
2 mBMC Watchdog Timer Internal mBMC timer Turns power OFF, or power cycle
3 Platform Event Filtering PEF Turns power OFF, or power cycle
4 Command Routed through command processor Turns power ON or OFF, or power cycle
5 Power state retention Implemented via mBMC internal logic Turns power ON when AC power returns
6 Chipset sleep S5 Turns power ON or OFF
5.3.2 System Reset Control
5.3.2.1 Reset Signal Output
The mBMC asserts the System Reset signal on the server board to perform a system reset. The
mBMC asserts the System Reset signal before powering the system up. After power is stable
(as indicated by the power subsystem Power Good signal), the mBMC sets the processor
enable state as appropriate and de-asserts the System Reset signal, taking the system out of
reset.