Intel SE7525GP2 - Manual (Page 5)

Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
Revision 2.0 5
3.3.1.2 MCH Memory Sub-System Overview..................................................................34
3.3.1.3 PCI
Express*.........................................................................................................34
3.3.1.4 Hub Interface ........................................................................................................35
3.4 Intel® 6300ESB ICH .............................................................................................. 35
3.4.1 PCI Interface.......................................................................................................... 35
3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode).................... 36
3.4.3 SATA Controller..................................................................................................... 36
3.4.4 Low Pin Count (LPC) Interface .............................................................................. 36
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 36
3.4.6 Advanced Programmable Interrupt Controller (APIC) ........................................... 37
3.4.7 Universal Serial Bus (USB) Controller ................................................................... 37
3.4.8 RTC ....................................................................................................................... 37
3.4.9 GPIO...................................................................................................................... 37
3.4.10 Enhanced Power Management ............................................................................. 37
3.4.11 System Management Bus (SMBus 2.0)................................................................. 37
3.5 Memory Sub-System ............................................................................................. 38
3.5.1 Memory Sizing ....................................................................................................... 38
3.5.2 Memory Population................................................................................................ 39
3.5.3 I2C Bus .................................................................................................................. 42
3.5.4 Disabling DIMMs.................................................................................................... 42
3.5.5 Memory RASUM Features..................................................................................... 42
3.5.5.1 DRAM ECC – Intel ® x4 Single Device Data Correction (x4 SDDC).................43
3.5.5.2 Integrated Memory Scrub Engine.........................................................................43
3.5.5.3 Retry on Uncorrectable Error................................................................................43
3.5.5.4 Integrated Memory Initialization Engine..............................................................44
3.5.5.5 DIMM Sparing Function.......................................................................................44
3.6 I/O Sub-System ..................................................................................................... 45
3.6.1 PCI Subsystem ...................................................................................................... 45
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem ...............................................................45
3.6.1.2 P64-A: 64-bit, 66MHz PCI Subsystem.................................................................46
3.6.1.3 P64-Express4: x4 PCI-Express Bus Segment.......................................................46
3.6.1.4 P64-Express16: x16 PCI-Express bus segment ....................................................46
3.6.1.5 Scan
Order ............................................................................................................46
3.6.1.6 Resource Assignment............................................................................................46
3.6.1.7 Automatic IRQ Assignment..................................................................................46
3.6.1.8 Option ROM Support............................................................................................46
3.6.1.9 PCI
APIs ...............................................................................................................46
3.6.2 Split Option ROM................................................................................................... 47
3.6.3 Interrupt Routing .................................................................................................... 47
3.6.3.1 Legacy Interrupt Routing......................................................................................47
3.6.3.2 APIC Interrupt Routing.........................................................................................47
3.6.3.3 Legacy Interrupt Sources ......................................................................................47
3.6.3.4 Serialized
IRQ Support .........................................................................................48
3.6.3.5 IRQ Scan for PCIIRQ ...........................................................................................48
3.6.4 IDE Support ........................................................................................................... 51