Intel SE7525GP2 User Manual
Page 150
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Connector Definitions and Pin-Outs
Revision 2.0
150
Pin No
Pin Name
Pin No
Pin Name
Pin No Pin Name Pin No
Pin Name Pin No
Pin Name
C27 SMI#
H6 VSS
R1 VCC AA1 VCC
AD29
NC
C28 VCC
H7 VCC
R2 VSS
AA2 VSS
AD30
VCC
C29 VSS
H8 VSS
R3 VCC AA3 BSEL0 2
AD31 VSS
C30 VCC
H9 VCC
R4 VSS
AA4 VCC
AE2 VSS
C31 VSS
H23 VCC
R5 VCC AA5 VSSA AE3 VCC
D1 VCC
H24 VSS
R6 VSS
AA6 VCC
AE4 SMB_PRT
D2 VSS
H25 VCC
R7 VCC AA7 TESTHI4
AE5 TESTHI6
D3 VID2
H26 VSS
R8 VSS
AA8 D61#
AE6 SLP#
D4 STPCLK# H27 VCC
R9 VCC AA9 VSS
AE7 D58#
D5 VSS
H28 VSS
R23 VCC AA10
D54#
AE8 VCC
D6
INIT# H29
VCC
R24
VSS AA11
D53# AE9
D44#
D7 MCERR# H30 VSS
R25 VCC AA12
VTT AE10
D42#
D8
VCC H31
VCC
R26
VSS AA13
D48# AE11
VSS
D9 AP1#
J1 VSS
R27 VCC AA14
D49# AE12
DBI2#
D10
BR3# 1
J2 VCC
R28
VSS AA15
VSS AE13
D35#
D11 VSS
J3 VSS
R29 VCC AA16 D33#
AE14 VCC
D12 A29#
J4 VCC
R30 VSS
AA17 VSS
AE15 Reserved
D13 A25#
J5 VSS
R31 VCC AA1 D24#
AE16 Reserved
D14
VCC J6 VCC
T1 VSS AA19
D15# AE17
DP3#
D15 A18#
J7 VSS
T2 VCC AA20 VCC
AE18 VCC
D16
A17# J8 VCC
T3 VSS AA21
D11# AE19
DP1#
D17 A9#
J9 VSS
T4 VCC AA22 D10#
AE20 D28#
D18 VCC
J23 VSS
T5 VSS
AA23 VSS
AE21 VSS
D19 ADS#
J24 VCC
T6 VCC AA24 D6#
AE22 D27#
D20 BR0#
J25 VSS
T7 VSS
AA25 D3#
AE23 D22#
D21 VSS
J26 VCC
T8 VCC AA26 VCC
AE24 VCC
D22 RS1#
J27 VSS
T9 VSS
AA27 D1#
AE25 D19#
D23 BPRI#
J28 VCC
T23 VSS
AA28 NC
AE26 D16#
D24 VCC
J29 VSS
T24 VCC AA29 NC
AE27 VSS
D25 Reserved J30 VCC
T25 VSS
AA30 VSS
AE28 Reserved
D26 VSSSENSE
J31 VSS
T26 VCC AA31 VCC
AE29 Reserved
D27 VSS
K1 VCC
T27 VSS
AB1 VSS
AE30 NC
D28 VSS
K2 VSS
T28 VCC AB2 VCC
Notes:
1. These are “Reserved ” pins on the Intel
®
Xeon™ processor. In systems utilizing the Intel
Xeon processor,
the system designer must terminate these signals to the processor VTT.
2. Server boards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 200MHz.
3. The FC-mPGA2P package contains an extra pin (located at location AE30) compared to the INT-mPGA
package. This additional pin serves as a keying mechanism to prevent the FC-mPGA2P package from being
installed in the 603-pin socket. Since the additional contact for pin AE30 is electrically inert, the 604-pin
socket will not have a solder ball at this location.