Compaq 21264 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for 21264 Compaq
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 356 |
| Size: | 3.99 MB |
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Document Outline
- Table of Contents
- Figures
- Tables
- Preface
- Introduction
- Internal Architecture
- 2.1 21264/EV67 Microarchitecture
- 2.2 Pipeline Organization
- 2.3 Instruction Issue Rules
- 2.4 Instruction Retire Rules
- 2.5 Retire of Operate Instructions into R31/F31
- 2.6 Load Instructions to R31 and F31
- 2.7 Special Cases of Alpha Instruction Execution
- 2.8 Memory and I/O Address Space Instructions
- 2.9 MAF Memory Address Space Merging Rules
- 2.10 Instruction Ordering
- 2.11 Replay Traps
- 2.12 I/O Write Buffer and the WMB Instruction
- 2.13 Performance Measurement Support—Performance Counters
- 2.14 Floating-Point Control Register
- 2.15 AMASK and IMPLVER Instruction Values
- 2.16 Design Examples
- Hardware Interface
- Cache and External Interfaces
- 4.1 Introduction to the External Interfaces
- 4.2 Physical Address Considerations
- 4.3 Bcache Structure
- 4.4 Victim Data Buffer
- 4.5 Cache Coherency
- 4.6 Lock Mechanism
- 4.7 System Port
- 4.7.1 System Port Pins
- 4.7.2 Programming the System Interface Clocks
- 4.7.3 21264/EV67-to-System Commands
- 4.7.4 21264/EV67-to-System Commands Descriptions
- 4.7.5 ProbeResponse Commands (Command[4:0] = 00001)
- 4.7.6 SysAck and 21264/EV67-to-System Commands Flow Control
- 4.7.7 System-to-21264/EV67 Commands
- 4.7.8 Data Movement In and Out of the 21264/EV67
- 4.7.9 Nonexistent Memory Processing
- 4.7.10 Ordering of System Port Transactions
- 4.8 Bcache Port
- 4.9 Interrupts
- Internal Processor Registers
- 5.1 Ebox IPRs
- 5.2 Ibox IPRs
- 5.2.1 ITB Tag Array Write Register – ITB_TAG
- 5.2.2 ITB PTE Array Write Register – ITB_PTE
- 5.2.3 ITB Invalidate All Process (ASM=0) Register – ITB_IAP
- 5.2.4 ITB Invalidate All Register – ITB_IA
- 5.2.5 ITB Invalidate Single Register – ITB_IS
- 5.2.6 ProfileMe PC Register – PMPC
- 5.2.7 Exception Address Register – EXC_ADDR
- 5.2.8 Instruction Virtual Address Format Register — IVA_FORM
- 5.2.9 Interrupt Enable and Current Processor Mode Register – IER_CM
- 5.2.10 Software Interrupt Request Register – SIRR
- 5.2.11 Interrupt Summary Register – ISUM
- 5.2.12 Hardware Interrupt Clear Register – HW_INT_CLR
- 5.2.13 Exception Summary Register – EXC_SUM
- 5.2.14 PAL Base Register – PAL_BASE
- 5.2.15 Ibox Control Register – I_CTL
- 5.2.16 Ibox Status Register – I_STAT
- 5.2.17 Icache Flush Register – IC_FLUSH
- 5.2.18 Icache Flush ASM Register – IC_FLUSH_ASM
- 5.2.19 Clear Virtual-to-Physical Map Register – CLR_MAP
- 5.2.20 Sleep Mode Register – SLEEP
- 5.2.21 Process Context Register – PCTX
- 5.2.22 Performance Counter Control Register – PCTR_CTL
- 5.3 Mbox IPRs
- 5.3.1 DTB Tag Array Write Registers 0 and 1 – DTB_TAG0, DTB_TAG1
- 5.3.2 DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1
- 5.3.3 DTB Alternate Processor Mode Register – DTB_ALTMODE
- 5.3.4 Dstream TB Invalidate All Process (ASM=0) Register – DTB_IAP
- 5.3.5 Dstream TB Invalidate All Register – DTB_IA
- 5.3.6 Dstream TB Invalidate Single Registers 0 and 1 – DTB_IS0,1
- 5.3.7 Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0,1
- 5.3.8 Memory Management Status Register – MM_STAT
- 5.3.9 Mbox Control Register – M_CTL
- 5.3.10 Dcache Control Register – DC_CTL
- 5.3.11 Dcache Status Register – DC_STAT
- 5.4 Cbox CSRs and IPRs
- Privileged Architecture Library Code
- 6.1 PALcode Description
- 6.2 PALmode Environment
- 6.3 Required PALcode Function Codes
- 6.4 Opcodes Reserved for PALcode
- 6.5 Internal Processor Register Access Mechanisms
- 6.6 PALshadow Registers
- 6.7 PALcode Emulation of the FPCR
- 6.8 PALcode Entry Points
- 6.9 Translation Buffer (TB) Fill Flows
- 6.10 Performance Counter Support
- Initialization and Configuration
- 7.1 Power-Up Reset Flow and the Reset_L and DCOK_H Pins
- 7.2 Fault Reset Flow
- 7.3 Energy Star Certification and Sleep Mode Flow
- 7.4 Warm Reset Flow
- 7.5 Array Initialization
- 7.6 Initialization Mode Processing
- 7.7 External Interface Initialization
- 7.8 Internal Processor Register Power-Up Reset State
- 7.9 IEEE 1149.1 Test Port Reset
- 7.10 Reset State Machine
- 7.11 Phase-Lock Loop (PLL) Functional Description
- Error Detection and Error Handling
- 8.1 Data Error Correction Code
- 8.2 Icache Data or Tag Parity Error
- 8.3 Dcache Tag Parity Error
- 8.4 Dcache Data Single-Bit Correctable ECC Error
- 8.5 Dcache Store Second Error
- 8.6 Dcache Duplicate Tag Parity Error
- 8.7 Bcache Tag Parity Error
- 8.8 Bcache Data Single-Bit Correctable ECC Error
- 8.9 Memory/System Port Single-Bit Data Correctable ECC Error
- 8.10 Bcache Data Single-Bit Correctable ECC Error on a Probe
- 8.11 Double-Bit Fill Errors
- 8.12 Error Case Summary
- Electrical Data
- Thermal Management
- Testability and Diagnostics
- Alpha Instruction Set
- 21264/EV67 Boundary-Scan Register
- Serial Icache Load Predecode Values
- PALcode Restrictions and Guidelines
- D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
- D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group
- D.3 Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group
- D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read- Modify-Write
- D.5 Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ ITOF
- D.6 Restriction 9 : PALmode Istream Address Ranges
- D.7 Restriction 10: Duplicate IPR Mode Bits
- D.8 Restriction 11: Ibox IPR Update Synchronization
- D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM
- D.10 Restriction 13 : DTB Fill Flow Collision
- D.11 Restriction 14 : HW_RET
- D.12 Guideline 16 : JSR-BAD VA
- D.13 Restriction 17: MTPR to DTB_TAG0/DTB_PTE0/DTB_TAG1/ DTB_PTE1
- D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block a...
- D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode
- D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable
- D.17 Restriction 21: HW_RET/STALL After HW_MTPR ASN0/ASN1
- D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1
- D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag
- D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
- D.21 Restriction 25: HW_MTPR ITB_IA After Reset
- D.22 Guideline 26: Conditional Branches in PALcode
- D.23 Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode
- D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads
- D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode
- D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR
- D.27 Restriction 31 : I_CTL[VA_48] Update
- D.28 Restriction 32 : PCTR_CTL Update
- D.29 Restriction 33 : HW_LD Physical/Lock Use
- D.30 Restriction 34 : Writing Multiple ITB Entries in the Same PALcode Flow
- D.31 Guideline 35 : HW_INT_CLR Update
- D.32 Restriction 36 : Updating I_CTL[SDE]
- D.33 Restriction 37 : Updating VA_CTL[VA_48]
- D.34 Restriction 38 : Updating PCTR_CTL
- D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow
- D.36 Restriction 40: Scrubbing a Single-Bit Error
- D.37 Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch Block
- D.38 Restriction 42: Updating VA_CTL, CC_CTL, or CC IPRs
- D.39 Restriction 43: No Trappable Instructions Along with HW_MTPR
- D.40 Restriction 44: Not Applicable to the 21264/EV67
- D.41 Restriction 45: No HW_JMP or JMP Instructions in PALcode
- D.42 Restriction 46: Avoiding Live locks in Speculative Load CRD Handlers
- D.43 Restriction 47: Cache Eviction for Single-Bit Cache Errors
- D.44 Restriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity
- 21264/EV67-to-Bcache Pin Interconnections
- Glossary
- Index