Compaq 21264 - Manual (Page 130)

4–42 Cache and External Interfaces Alpha 21264/EV67 Hardware Reference Manual
Bcache Port
4.7.10.2 System Probes and SysDc Commands
Ordering of cache transactions at the system serialization point must be reflected in the
21264/EV67 cache system. Table 4–34 shows the rules that a system must follow to
control the order of cache status update within the 21264/EV67 cache structures
(including the VAF) at the 21264/EV67 pins.
4.8 Bcache Port
The 21264/EV67 supports a second-level cache (Bcache) with 64-byte blocks. The
Bcache size can be 1MB, 2MB, 4MB, 8MB, or 16MB. The Bcache port has a 144-bit
data bus that is used for data transfers between the 21264/EV67 and the Bcache. All
Bcache control and address signal lines are clocked synchronously on Bcache clock cycle
boundaries.
Table 4–34 Rules for System Control of Cache Status Update Order
First Second Rule
Probe Probe To control the sequence of cache status updates between probes, systems
can present the probes in order to the 21264/EV67, and the 21264/EV67
will update the appropriate cache state (including the VAF) in order.
Probe SysDc MAF To ensure that a probe updates the internal cache status before a SysDc
MAF transaction (including fills and ChangeToDirtySuccess commands),
systems must wait for the probe response before presenting the SysDc
MAF command to the 21264/EV67. To ensure that a probe updates a VAF
entry before a SysDc VAF (release buffer), systems must wait for the
probe response.
Probe SysDc VAF Same as Probe/SysDc MAF, above.
SysDc MAF Probe To ensure that a SysDc MAF command updates the 21264/EV67 cache
system before a probe to the same address, systems must deliver the D1
(the second QW of data delivered to the 21264/EV67) before or in the
same cycle as the A3 of the probe (the last cycle of the 4-cycle probe com-
mand). This rule also applies to ChangeToDirtySuccess commands that
have a virtual D0 and D1 transaction.
SysDc MAF SysDc MAF SysDc MAF transactions can be ordered into the 21264/EV67 by ordering
them appropriately at the 21264/EV67 interface.
SysDc MAF SysDc VAF SysDc MAF transactions and SysDc VAF transactions cannot interact
within the 21264/EV67 because the 21264/EV67 does not generate MAF
transactions to the same address as existing VAF transactions.
SysDc VAF Probe To ensure that a SysDc VAF invalidates a VAF entry before a probe to the
same address, the SysDc VAF command must precede the first cycle of the
4-cycle probe command.
SysDc VAF SysDc MAF SysDc MAF transactions and SysDc VAF transactions cannot interact
within the 21264/EV67 because the 21264/EV67 does not generate MAF
transactions to the same address as existing VAF transactions.
SysDc VAF SysDc VAF SysDc VAF transactions can be ordered into the 21264/EV67 by ordering
them appropriately at the 21264/EV67 interface.