Compaq 21264 - Manual (Page 278)

A–12 Alpha Instruction Set Alpha 21264/EV67 Hardware Reference Manual
Opcode Summary
Table A–7 Independent Floating-Point Instruction Function Codes
A.6 Opcode Summary
Table A–8 lists all Alpha opcodes from 00 (CALL_PAL) through 3F (BGT). In the
table, the column headings that appear over the instructions have a granularity of 8
16
.
The rows beneath the Offset column supply the individual hexadecimal number to
resolve that granularity.
If an instruction column has a 0 in the right (low) hexadecimal digit, replace that 0 with
the number to the left of the backslash (\) in the Offset column on the instruction’s row.
If an instruction column has an 8 in the right (low) hexadecimal digit, replace that 8
with the number to the right of the backslash in the Offset column.
For example, the third row (2/A) under the 10
16
column contains the symbol INTS*,
representing the all-integer shift instructions. The opcode for those instructions would
then be 12
16
because the 0 in 10 is replaced by the 2 in the Offset column. Likewise, the
third row under the 18
16
column contains the symbol JSR*, representing all jump
instructions. The opcode for those instructions is 1A because the 8 in the heading is
replaced by the number to the right of the backslash in the Offset column. The
instruction format is listed under the instruction symbol.
Mnemonic None /V /SV
CPYS 020 — —
CPYSE
022
— —
CPYSN
021
— —
CVTLQ
010
— —
CVTQL
030 130 530
FCMOVEQ
02A
— —
FCMOVGE
02D
— —
FCMOVGT
02F
— —
FCMOVLE
02E
— —
FCMOVLT
02C
— —
MF_FPCR
025
— —
MT_FPCR
024
— —
Table A–8 Opcode Summary
Offset 00 08 10 18 20 28 30 38
0/8 PAL*
(pal) LDA
(mem) INTA*
(op) MISC*
(mem) LDF
(mem) LDL
(mem) BR
(br) BLBC
(br)
1/9 Res LDAH
(mem) INTL*
(op) \PAL\ LDG
(mem) LDQ
(mem) FBEQ
(br) BEQ
(br)
2/A LDBU Res INTS*
(op) JSR*
(mem) LDS
(mem) LDL_L
(mem) FBLT
(br) BLT
(br)