Compaq 21264 - Manual (Page 212)

7–4 Initialization and Configuration Alpha 21264/EV67 Hardware Reference Manual
Power-Up Reset Flow and the Reset_L and DCOK_H Pins
In addition, as power is being ramped, Reset_L must be asserted — this allows the
21264/EV67 to reset internal state. Once the target voltage levels are attained, systems
should assert DCOK_H. This indicates to the 21264/EV67 that internal logic functions
can be evaluated correctly and that the power-up sequence should be continued. Prior to
DCOK_H being asserted, the logic internal to the 21264/EV67 is being reset and the
internal clock network is running (either clocked by the PLL VCO, which is at a nomi-
nal speed, or by ClkIn_H, if the PLL is bypassed).
The reset state machine is in state WAIT_SETTLE.
7.1.2 Clock Forwarding and System Clock Ratio Configuration
When DCOK_H is asserted, the 21264/EV67 samples several pins and latches in some
initialization state, including the value of the PLL Y
div
divisor, which specifies the
ratio of the system clock to the internal clock (see Section 7.11.2.3), and enables the
charge pump on the phase-locked loop.
SysAddOut_L[14:0] Initially, during power-up reset, state
is not defined. If not during power-
up, preserves previous state. Then,
after the clock forward reset period
(as the external clocks start), signal
driven to NZNOP until the reset
state machine enters RUN, when it
is driven to NOP. SysDataOutValid_L NA (input)
SysAddOutClk_L Tristated SysFillValid_L NA (input)
SysCheck_L[7:0] Tristated SysVref NA
(I_DC_REF)
SysData_L[63:0] Tristated
Clocks
ClkFwdRst_H NA (input) FrameClk_x NA (input)
ClkIn_H
ClkIn_L NA (input) PLL_VDD NA
(I_DC_REF)
EV6Clk_H
EV6Clk_L NA (input)
Miscellaneous
DCOK_H Must be deasserted until dc voltage
reaches proper operating level. Tck_H NA (input)
PllBypass_H NA (input) Tdi_H NA (input)
Reset_L NA (input) Tdo_H Unspecified
SromClk_H Tristated TestStat_H Tristated
SromData_H NA (input) Tms_H NA (input)
SromOE_L Tristated Trst_L NA (input)
Table 7–2 Signal Pin Reset State (Continued)
Signal Reset State Signal Reset State