D.27 restriction 31 : i_ctl[va_48] update, D.28 restriction 32 : pctr_ctl update, D.27 – Compaq 21264 User Manual

Page 315: Restriction 31 : i_ctl[va_48] update, D–17, D.28, Restriction 32 : pctr_ctl update, D.28 restriction 32 : pctr_ctl update

Alpha 21264/EV67 Hardware Reference Manual

PALcode Restrictions and Guidelines

D–17

Restriction 31 : I_CTL[VA_48] Update

sys__cbox_over6:

; block 6

beq

p6, sys__cbox_over8

; branch if done

bis

r31, r31, r31

; nop

r31, sys__cbox_over7

; go to block 7

sys__cbox_touch6:

;

r31, sys__cbox_touch7

; touch block 7

sys__cbox_over7:

; block 7

bis

p7, r31, p20

; save before shifting

sll

p7, #6, p7

; shift data 6 bits left

r31, sys__cbox_over2

; do next shift

sys__cbox_touch7:

;

r31, sys__cbox_touch8

; touch block 8

sys__cbox_over8:

; block 8

beq

r31, sys__cbox_cbox_done

; predict not taken

PVC_VIOLATE <1006>

r31, .-4

; predict back to infinite loop

bis

r31, r31, r31

;

sys__cbox_touch8:

;

r31, sys__cbox_over1

; now start executing the shifts

sys__cbox_cbox_done:

; now restore i_ctl

hw_mfpr p6, EV6__I_CTL

; (4,0L) get i_ctl

lda

p4, <3@EV6__I_CTL__SBE__S>(r31)

; sbe bits

p6, p4, p4

; set SBE bits

bis

r31, r31, r31

hw_mtpr p4, EV6__I_CTL

; (4,0L) restore i_ctl

PVC_JSR cbox, bsr=1, dest=1

hw_ret_stall (p5)

; return to caller with stall

D.27 Restriction 31 : I_CTL[VA_48] Update

The VA_48 virtual address format cannot be changed while executing a JSR, JMP,
GOTO, JSR_COROUTINE, or HW_RET instruction. A simple method of ensuring
that the address does not change is to write I_CTL twice, in two separate fetch blocks,
with the same data. The second write will stall the pipeline and ensure that the mode
cannot change, even down a mispredicted path, while a following JSR type instruction
might be using the address comparison logic.

D.28 Restriction 32 : PCTR_CTL Update

The performance counter must not be left in a state near overflow. If counting is dis-
abled, the counters may produce multiple overflow signals if the counter output is not
updated due to the counter being disabled. A repeated overflow signal with counters
disabled can block other incoming interrupt requests while the overflow state persists.
To avoid this situation, reads or writes to the counters should not leave a value near
overflow. In normal operation, with counters enabled, a counter overflow will produce
an overflow pulse, clear the counter, and produce a performance counter interrupt.
Interrupts can only be blocked for one cycle.