Compaq 21264 - Manual (Page 349)

Alpha 21264/EV67 Hardware Reference Manual Index–5
ECC
64-bit data and check bit code , 8–2
Dcache data single-bit correctable errors , 8–3
for system data bus , 8–2
memory/system port single-bit correctable
errors , 8–7
store instructions , 8–4
ENABLE_EVICT Cbox CSR , 4–23 , 5–39
ENABLE_PROBE_CHECK Cbox CSR , 8–2
defined , 5–35
ENABLE_STC_COMMAND Cbox CSR, defined ,
5–35
Energy star certification , 7–9
Error case summary , 8–9
Error correction code. See ECC
Error detection mechanisms , 8–1
EV6Clk_x signal pins , 3–4
Evict, 21264/EV67 command , 4–13 , 4–22 , 4–39
EVICT_ENABLE Cbox CSR , 7–13
EXC_ADDR exception address register , 5–8
after fault reset , 7–8
at power-on reset state , 7–15
EXC_SUM exception summary register , 5–13
at power-on reset state , 7–15
Exception and interrupt logic , 2–8
Exception condition summary , A–15
External cache and system interface unit. See Cbox
External convention , xxi
External interface initialization , 7–14
EXTEST public instruction , B–1
F
F31
load instructions with , 2–23
retire instructions with , 2–22
Fast data disable mode , 4–33
Fast data mode , 4–30 , 4–31
FAST_MODE_DISABLE Cbox CSR , 4–30
defined , 5–34
Fault reset flow , 7–8
Fault reset sequence of operations , 7–9
FAULT_RESET reset machine state , 7–18
Fbox
described , 2–10
executed in pipeline , 2–16
FEN fault , 6–13
FetchBlk, 21264/EV67 command , 4–22 , 4–39
system probes, with , 4–41
FetchBlkSpec, 21264/EV67 command , 4–22 , 4–39
Field notation convention , xxi
Floating-point arithmetic trap, pipeline abort delay
with , 2–16
Floating-point control register , 2–36
PALcode emulation of , 6–11
Floating-point execution unit. See Fbox
Floating-point instructions
IEEE , A–9
independent , A–11
VAX , A–11
Floating-point issue queue , 2–7
Forwarding clock pin groupings , E–1
FPCR. See Floating-point control register
FQ. See Floating-point issue queue
FrameClk_x signal pins , 3–5 , 4–30
G
GCLK , 7–19
Global predictor , 2–4
H
Heat sink center temperature , 10–1
Heat sink specifications , 10–3
HW_INT_CLR hardware interrupt clear register ,
5–12
at power-on reset state , 7–15
updating , D–18
HW_LD PALcode instruction , 6–3 , A–9 , D–18
HW_MFPR PALcode instruction , 6–6 , A–9
HW_MTPR PALcode instruction , 6–6 , A–9
HW_REI PALcode instruction , A–9
HW_RET PALcode instruction , 6–5
HW_ST PALcode instruction , 6–4 , A–9
I
I/O address space
instruction data merging , 2–29
load instruction data merging , 2–28
load instructions with , 2–28
store instructions with , 2–29
I/O write buffer , 2–11
defined , 2–32