Epson S1C88650 - Manual (Page 99)

S1C88650 TECHNICAL MANUAL EPSON 91
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
5.10.5 Interrupt function
The 16-bit programmable timer can generate an
interrupt with the compare match signal and
underflow signal of each timer.
Figure 5.10.5.1 shows the configuration of the 16-
bit programmable timer interrupt circuit.
The compare match signal and underflow signal of
each timer set the corresponding interrupt factor
flag to "1". At that point, the interrupt is generated.
The interrupt can also be prohibited by setting the
interrupt enable register to correspond with the
interrupt factor flag.
Furthermore, the priority level of the interrupt for
the CPU can be set to an optional level (0–3) using
the interrupt priority register.
Table 5.10.5.1 shows the interrupt factor flags,
interrupt enable registers and interrupt priority
registers corresponding to the interrupt factors.
In the 8-bit mode, the compare match interrupt
factor flag and underflow interrupt factor flag are
individually set to "1" by the timers.
In the 16-bit mode, the interrupt factor flags of
Timer(H) are set to "1" by the compare match and
underflow in 16 bits.
Refer to Section 5.14, "Interrupt and Standby
Status", for details of the interrupt control registers
and operations subsequent to interrupt generation.
The exception processing vector addresses for the 16-
bit programmable timer interrupt are set as follows:
Timer 0 underflow interrupt: 000016H
Timer 0 compare match interrupt: 000018H
Timer 1 underflow interrupt:
00001AH
Timer 1 compare match interrupt: 00001CH
Timer 2 underflow interrupt:
00001EH
Timer 2 compare match interrupt: 000020H
Timer 3 underflow interrupt:
000022H
Timer 3 compare match interrupt: 000024H
Timer 4 underflow interrupt:
00003CH
Timer 4 compare match interrupt: 00003EH
Timer 5 underflow interrupt:
000040H
Timer 5 compare match interrupt: 000042H
Timer 6 underflow interrupt:
000044H
Timer 6 compare match interrupt: 000046H
Timer 7 underflow interrupt:
000048H
Timer 7 compare match interrupt: 00004AH
Table 5.10.5.1 Interrupt control registers
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Interrupt factor
Interrupt factor flag
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Name
FTU0
FTC0
FTU1
FTC1
FTU2
FTC2
FTU3
FTC3
FTU4
FTC4
FTU5
FTC5
FTU6
FTC6
FTU7
FTC7
Address·Dx
00FF29H·D0
00FF29H·D1
00FF29H·D2
00FF29H·D3
00FF29H·D4
00FF29H·D5
00FF29H·D6
00FF29H·D7
00FF2EH·D0
00FF2EH·D1
00FF2EH·D2
00FF2EH·D3
00FF2EH·D4
00FF2EH·D5
00FF2EH·D6
00FF2EH·D7
Interrupt enable register
Name
ETU0
ETC0
ETU1
ETC1
ETU2
ETC2
ETU3
ETC3
ETU4
ETC4
ETU5
ETC5
ETU6
ETC6
ETU7
ETC7
Address·Dx
00FF25H·D0
00FF25H·D1
00FF25H·D2
00FF25H·D3
00FF25H·D4
00FF25H·D5
00FF25H·D6
00FF25H·D7
00FF2CH·D0
00FF2CH·D1
00FF2CH·D2
00FF2CH·D3
00FF2CH·D4
00FF2CH·D5
00FF2CH·D6
00FF2CH·D7
Interrupt priority register
Name
PPT0
PPT1
PPT2
PPT3
PPT4
PPT5
PPT6
PPT7
Address·Dx
00FF21H·D2
00FF21H·D3
00FF21H·D4
00FF21H·D5
00FF2AH·D0
00FF2AH·D1
00FF2AH·D2
00FF2AH·D3