Epson S1C88650 - Manual (Page 12)

4 EPSON S1C88650 TECHNICAL MANUAL
1 INTRODUCTION
1.3.2 Pin description
Table 1.3.2.1 S1C88650 pin description
Pin No.
V DD
V SS
V D1
V D2
V C1– V C5
CA–CG
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00–K02
K03/BREQ
K04/EXCL0
K05/EXCL1
K06/EXCL2
K07/EXCL3
R00–R07/A0–A7
R10–R17/A8–A15
R20–R23/A16–A19
R24/RD
R25/WR
R30–R32/CE0–CE2
R33 (BACK)
P00–P07/D0–D7
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14/TOUT0/TOUT1
P15/TOUT2/TOUT3
P16/FOUT
P17/TOUT2/TOUT3
COM0–COM31
SEG0–SEG125
RESET
TEST
TEST
Pin name In/Out Function
131, 189
67, 134, 195, 253
135
113
125–121
120–114
136
137
132
133
140
148–146
145
144
143
142
141
165–172
173–180
181–184
185
186
187, 188, 196
197
164–157
156
155
154
153
152
151
150
149
198–213, 112–97
214–252, 4–61,
68–96
139
138
3
–
–
–
–
–
–
I
O
I
O
I
I
I
I
I
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
–
Power supply (+) terminal
Power supply (GND) terminal
Internal logic system and oscillation system voltage regulator output terminals
LCD circuit power voltage booster output terminal
LCD drive voltage output terminals
LCD and power voltage booster capacitor connection terminals
OSC1 oscillation input terminal (select crystal/CR oscillation by mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option)
OSC3 oscillation output terminal
MCU/MPU mode setup terminal
Input terminals (K00–K02)
Input terminal (K03) or bus request signal input terminal (BREQ)
Input terminal (K04) or programmable timer external clock input terminal (EXCL0)
Input terminal (K05) or programmable timer external clock input terminal (EXCL1)
Input terminal (K06) or programmable timer external clock input terminal (EXCL2)
Input terminal (K07) or programmable timer external clock input terminal (EXCL3)
Output terminals (R00–R07) or address bus (A0–A7)
Output terminals (R10–R17) or address bus (A8–A15)
Output terminals (R20–R23) or address bus (A16–A19)
Output terminal (R24) or read signal output terminal (RD)
Output terminal (R25) or write signal output terminal (WR)
Output terminals (R30–R32) or chip enable signal output terminals (CE0–CE2)
Output terminal (R33) or bus acknowledge signal output terminal (BACK)
I/O terminals (P00–P07) or data bus (D0–D7)
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminal (P14)
or programmable timer underflow signal output terminal (TOUT0/TOUT1)
I/O terminal (P15)
or programmable timer underflow signal output terminal (TOUT2/TOUT3)
I/O terminal (P16) or clock output terminal (FOUT)
I/O terminal (P17)
or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3)
LCD common output terminals
LCD segment output terminals
Initial reset input terminal
Test input terminal
Test terminal (open during normal operation)