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3 control of watchdog timer, 4 programming notes – Epson S1C88650 User Manual

Page 48

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EPSON

S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)

5.3.3 Control of watchdog timer

Table 5.3.3.1 shows the control bits for the watchdog timer.

Table 5.3.3.1 Watchdog timer control bits

SR R/W

Address Bit

Name

Function

Comment

1

0

00FF40 D7

D6

D5

D4

D3

D2

D1

D0

WDEN

FOUT2

FOUT1

FOUT0

WDRST

TMRST

TMRUN

Constantly "0" when

being read

1

0

0

0

0

0

R/W

R/W

R/W

R/W

R/W

W

W

R/W

Enable

On

Reset

Reset

Run

Disable

Off

No operation

No operation

Stop

Watchdog timer enable

FOUT frequency selection

FOUT output control

Watchdog timer reset

Clock timer reset

Clock timer Run/Stop control

FOUTON

FOUT2

1
1
1
1
0
0
0
0

FOUT1

1
1
0
0
1
1
0
0

FOUT0

1
0
1
0
1
0
1
0

Frequency

f

OSC1

/ 1

f

OSC1

/ 2

f

OSC1

/ 4

f

OSC1

/ 8

f

OSC3

/ 1

f

OSC3

/ 2

f

OSC3

/ 4

f

OSC3

/ 8

WDEN: 00FF40H•D7

Selects whether the watchdog timer is used
(enabled) or not (disabled).

When "1" is written: Enabled
When "0" is written: Disabled
Reading:

Valid

When "1" is written to the WDEN register, the
watchdog timer starts count operation. When "0" is
written, the watchdog timer does not count and

______

does not generate the interrupt (NMI).
At initial reset, this register is set to "1".

WDRST: 00FF40H•D2

Resets the watchdog timer.

When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading:

Constantly "0"

By writing "1" to WDRST, the watchdog timer is
reset, after which it is immediately restarted.
Writing "0" will mean no operation.
Since WDRST is for writing only, it is constantly set
to "0" during readout.

5.3.4 Programming notes

(1) When the watchdog timer is being used, the

software must reset it within the cycles selected
by mask option.

(2) Do not execute the SLP instruction for 2 msec

______

after a NMI interrupt has occurred (when f

OSC1

is 32.768 kHz).

(3) Because the watchdog timer is set in operation

state by initial reset, set the watchdog timer to
disabled state (not used) before generating an

______

interrupt (NMI) if it is not used.

(4)

______

The NMI generation cycles in the watchdog
timer mask option list represent maximum
values. A maximum minus (cycle> / 4) seconds of error occurs depending
on the watchdog timer reset timing. For
example, when 131072/f

OSC1

is selected by

______

mask option, the actual NMI generation cycle is
within the range of 98304/f

OSC1

to 131072/f

OSC1

seconds.