Altera JNEye User Manual
Page 153
Stratix V GX transmitter has a 4-tap FIR to compensate for channel effects. The PCI Express 8G receiver
has CTLE and a 1-Tap DFE per PCI-SIG definition.
To accomplish these goals, set up a transmitter model, a receiver model, and a link with the following
parameters:
• Data rate: 8 Gbps
• Test pattern: PRBS-23
• BER target: BER < 10
–12
• Stratix V GX transmitter
• V
OD
: 800 mV (VOD Level = 40)
• Edge rate: Per Stratix V GX characteristics
• 4-Tap TX FIR (1 pre-tap and 2 post-taps)
• Stratix V GX package model (embedded)
• PLL: ATX (LC) set to low bandwidth
• Output Jitter: Retrieved from the Altera Characterization Database (embedded in JNEye; contact
your Altera representative to enable this function)
• DCD = ~0.012 UI
• BUJ = ~0.032 UI
• RJ = ~1.00 ps
RMS
(8 Gbps, BER < 10
–12
)
• Receiver
• CTLE:
• Programmable with 6 dB~12 dB boost at 4 GHz
• Per PCI-SIG specifications
• 1-tap DFE
• PCI-SIG receiver package model (12-port S-parameter model from PCI-SIG)
• CDR: Generic binary CDR with high loop bandwidth ~26 MHz
• Receiver Jitter:
• DJ = ~7 ps
• RJ = ~1.55 ps
RMS
(at BER < 10
–12
)
3-2
Methodology
UG-1146
2015.05.04
Altera Corporation
Tutorial: PCI Express 8GT