Altera JNEye User Manual
Page 102
PLL Type: Enable
PLL Bandwidth: SVGX_TXPLL_High
TX Pre-emphasis/FIR Mode: Off
Jitter & Noise Configuration:
DJ = 8.53333 ps
DCD = 0 ps
BUJ = 0 ps
RJ = 0.74 ps-rms
SJ = 0 ps at 0 MHz
DN = 0 mV
BUN = 0 mV
RN = 0 mV-rms
Receiverr: Arria V GZ
Package: Arria V GZ
Supply Voltage: 1V
CTLE Mode: Auto
CDR Type: Alexander
CDR Bandwidth: SVGX_CDR_Medium_BW
DFE Enable: Enable
DFE Mode: Auto
Transmitter Jitter & Noise Configuration: No Jitter and Noise
Channel Configuration:
[1] File Name: S12p_pin2pin_642010.s12p
Channel Type: Loss
Port Configuration: 2
Lane Number: 2
Port Number: 12
Aggressor ID: 1
Aggressor Relative Amplitude: 1
Aggressor Delay: 0
************************************************************************
************************ Simulation Record *****************************
Transmitter Reference Clock Random Jitter= 0 ps-RMS
Test Point 1 with Ideal Clock
Stratix V GX TX Pre-emphasis: Pre-Tap 1 = 0.00 Post-Tap 1 = -0.00 Post-
Tap 2 = 0.00
Eye Width=0.59UI (57.481ps), Eye Height= 789.36mV, Jitter(p-p)=0.41UI
(39.489ps)
Random Jitter= 0.883382 ps-RMS
Test Point 1 with Recovered Clock
Stratix V GX TX Pre-emphasis: Pre-Tap 1 = 0.00 Post-Tap 1 = -0.00 Post-
Tap 2 = 0.00
Eye Width=0.74UI (71.875ps), Eye Height= 807.31mV, Jitter(p-p)=0.26UI
(25.095ps)
Random Jitter= 0.840335 ps-RMS
Bit Errors = 0
Test Point 2
Eye Width=0.00UI ( 0.000ps), Eye Height= 0.00mV, Jitter(p-p)=1.00UI
(96.970ps)
Random Jitter= 0.883382 ps-RMS
Test Point 3 with Ideal Clock
CTLE Setting: Arria V GZ CTLE DC=0dB AC=12 (Gain=14.4111dB) BW=12GHz
Vod=H (Auto Mode, Method = Area)
Eye Width=0.30UI (29.451ps), Eye Height= 146.21mV, Jitter(p-p)=0.70UI
(67.519ps)
Random Jitter= 0.883382 ps-RMS
Test Point 3 with Recovered Clock
CTLE Setting: Arria V GZ CTLE DC=0dB AC=12 (Gain=14.4111dB) BW=12GHz
2-96
JNEye Data Viewer Module
UG-1146
2015.05.04
Altera Corporation
Functional Description