Device speed grade support, Release information, Device speed grade support -6 – Altera Hybrid Memory Cube Controller User Manual
Page 9: Release information -6
Device Speed Grade Support
Table 1-4: Minimum Recommended Device Family Speed Grades
Altera recommends that you configure the HMC Controller IP core only in the device speed grades listed in the
table, or any faster (lower numbered) device speed grades that are available.
Altera does not support configuration of this IP core in slower (higher numbered) device speed grades.
Device Family
IP Core Variation: Lane Rate
10 Gbps
12.5 Gbps
Arria 10
E1, I1, E2, I2
E1, I1
Release Information
Table 1-5: HMC Controller IP Core Current Release Information
Item
Value
Version
15.0
Release Date
May 2014
Ordering Code
Full-width: IP-HMCSR15FW
Half-width: IP-HMCSR15HW
Vendor ID
6AF7
Product ID
Full-width: 0122
Half-width: 0128
1-6
Device Speed Grade Support
UG-01152
2015.05.04
Altera Corporation
About the Altera Hybrid Memory Cube Controller IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)