Hmc controller ip core signals, Application interface signals, Application request interface – Altera Hybrid Memory Cube Controller User Manual
Page 38: Hmc controller ip core signals -1, Application interface signals -1, Application request interface -1
HMC Controller IP Core Signals
4
2015.05.04
UG-01152
The HMC Controller IP core communicates with other design components through multiple interfaces.
The IP core has the following top-level signals:
on page 4-1
The HMC Controller IP core's HMC interface connects to the external HMC device's link interface and
main reset signal.
Signals on the Interface to the I2C Master
Your design must include an I
2
C master module that drives the HMC device I
2
C interface for link
initialization. This interface connects to the I
2
C module.
Control and Status Interface Signals
on page 4-10
Transceiver Reconfiguration Signals
on page 4-13
Signals on the Interface to the External PLLs
Application Interface Signals
The application interface supports easy access to the external HMC device by providing a simple data path
interface to specify memory read and write requests and to receive memory read and write responses. This
interface is also called the data path interface.
Related Information
Application Request Interface
The data path request interface, or application request interface, provides a 512-bit or 256-bit data bus
and dedicated signals for the application to provide HMC request packet field values to the HMC
Controller IP core. Full-width variations have a 512-bit data bus, and half-width variations have a 256-bit
data bus. The interface supports Write requests with payload sizes up to 128 bytes. In full-width
variations, the maximum payload size limits the interface to data bursts of 2 or fewer
core_clk
clock
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