Altera Hybrid Memory Cube Controller User Manual
Page 26
testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts
generated with the testbench.
Figure 2-9: Simulation in Quartus II Design Flow
Post-fit timing
simulation netlist
Post-fit timing
simulation
(3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
Note: Post-fit timing simulation is not supported for 28nm and later device architectures. Therefore, the
HMC Controller IP core does not support post-fit timing simulation.
Altera IP supports a variety of simulation models, including simulation-specific IP functional simulation
models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The
models support fast functional simulation of your IP core instance using industry-standard VHDL or
Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can
simulate that model.
Note: Use the simulation models only for simulation and not for synthesis or any other purposes. Using
these models for synthesis creates a nonfunctional design.
If you use an HMC BFM to simulate your HMC Controller IP core, ensure that you set the BFM
parameters to match the features of your HMC Controller IP core and design. For example, confirm that
you set the BFM memory size (2G or 4G) to match the address space that you expect your design to
access, and that you set the BFM to communicate correctly with the HMC Controller IP core in Response
Open Loop Mode. You must also set the BFM to send Write response packets for non-posted Write
transactions received, because the HMC Controller IP core does not support the
TGA
field.
Related Information
UG-01152
2015.05.04
Simulating Altera IP Cores in other EDA Tools
2-17
Getting Started with the HMC Controller IP Core
Altera Corporation