Hmc controller ip core supported features, Hmc controller ip core supported features -2 – Altera Hybrid Memory Cube Controller User Manual
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Related Information
The HMC specification is available for download from the Hybrid Memory Cube Consortium web page.
HMC Controller IP Core Supported Features
The Altera HMC Controller IP core offers the following features:
• Communicates through Altera high-speed transceivers with an external HMC device compliant with
the HMC Specification 1.1.
• Communicates with the HMC device at per-lane rates of 10 Gbps or 12.5 Gbps.
• Features Avalon
®
Memory-Mapped (Avalon-MM) interface to access control and status registers.
• Supports selection of a full-width variation that connects to 16 lanes of an HMC device, or a half-width
variation that connects to 8 lanes of an HMC device.
• Full-width IP core variations feature a simple 512-bit client data interface, and support memory
READ and WRITE transactions with payloads of 16, 32, 64, and 128 bytes.
• Half-width IP core variations feature a simple 256-bit client data interface, and support memory
READ and WRITE transactions with payloads of 16, 32, 48, 64, 80, 96, 112, and 128 bytes.
• Supports posted and non-posted versions of ATOMIC transactions, BIT WRITE transactions, and
WRITE transactions.
• Supports MODE READ and MODE WRITE transactions.
• Supports Response Open Loop Mode for receive (RX) flow control to decrease device resource
requirements.
• Supports token-based transmit (TX) flow control.
• Supports poisoned packets.
• Supports reordering of transceiver lanes for board-design flexibility.
• Supports link training sequence and provides word alignment, lane alignment, and transceiver status
information in real time.
• Provides fast simulation support.
• Provides real-time error statistics.
• Provides hardware reset control.
• Optionally supports ADME direct access to transceiver registers through the Quartus II System
Console.
• Provides option to include ECC support in all M20K memory blocks configured in the IP core.
To support multi-link connection to the HMC device in your design, you can configure multiple HMC
Controllers to communicate with the same HMC device through separate HMC links.
For the detailed HMC specification refer to the HMC Specification 1.1.
Related Information
The HMC Specification 1.1 is available on the Hybrid Memory Cube Consortium website.
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HMC Controller IP Core Supported Features
UG-01152
2015.05.04
Altera Corporation
About the Altera Hybrid Memory Cube Controller IP Core