Altera Hybrid Memory Cube Controller User Manual
Page 59
Bits
Field Name
Type
Value on
Reset
Description
8
Retry Buffer
Full
W1C 0x0
The IP core sets this interrupt bit if the Retry buffer fills.
When the Retry buffer is full, the IP core does not send any
additional Read or Write requests. This situation is not an
error condition, but it may indicate a reduction in perform‐
ance.
7
Reserved
RO
0x0
6
RX Error
Response
Overflow
W1C 0x0
The IP core sets this interrupt bit if too many Error
Response packets are received before they are read from the
ERROR_RESPONSE
register. If overflow occurs, the IP core
drops incoming Error Response packets until space is again
available in the Error Response queue.
5
RX Error
Response
W1C 0x0
The IP core sets this interrupt bit if the IP core receives an
Error Response packet.
4
Fatal Error
W1C 0x0
The IP core sets this interrupt bit if it makes three or more
successive retry attempts that are unsuccessful.
3
Remote Error
W1C 0x0
The IP core sets this interrupt bit if it receives a valid IRTRY
(StartRetry) sequence, indicating the HMC device detected
an error.
2
SEQ Error
W1C 0x0
The IP core sets this interrupt bit if it receives a packet with a
SEQ
field value that is not a +1 increment from the
SEQ
field
value of the previous packet it received.
1
LNG/DLN Error
W1C 0x0
The IP core sets this interrupt bit if it receives a packet with
unequal or invalid values in the
LNG
(packet length) and
DLN
(duplicate length) fields.
0
CRC Error
W1C 0x0
The IP core sets this interrupt bit to the value of 1 if it detects
an error in the CRC of a packet it receives.
Table 5-9: HMC Controller IP Core INTERRUPT_ENABLE Register at Offset 0x24
Each bit in this register enables the corresponding interrupt in the
INTERRUPT_STATUS
register at offset 0x20. For
each register bit:
• If the bit has the value of 0, the interrupt is disabled.
• If the bit has the value of 1, and the
GlobalEnable
bit of the
GLOBAL_INTERRUPT_ENABLE
register at offset 0x28
has the value of 1, the interrupt is enabled.
Bits
Field Name
Type
Value on
Reset
Description
31:
16
Reserved
RO
0x0000
15
Response Queue
Uncorrectable
ECC Error
Enable
RW
0x0
Enables
Response Queue Uncorrectable ECC Error
interrupt.
UG-01152
2015.05.04
Interrupt Related Registers
5-7
HMC Controller IP Core Register Map
Altera Corporation