Altera Hybrid Memory Cube Controller - Manual (Page 32)

External PLL Interface
The HMC Controller IP core requires that you generate one or more external transceiver PLL IP cores
and connect one of the PLL IP cores to each HMC Controller IP core lane.
If you do not generate and connect the transceiver PLL IP cores, the HMC Controller IP core does not
function correctly in hardware.
Related Information
• Adding the External PLL on page 2-11
Describes how to generate an external transceiver PLL IP core, including parameter requirements.
• Signals on the Interface to the External PLLs on page 4-15
• HMC Controller IP Core Example Design on page 6-1
The HMC Controller example design provides an example of how to connect external PLLs to your
HMC Controller IP core.
• Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver PLLs and clock network.
Transceiver Reconfiguration Interface
The transceiver reconfiguration interface provides access to the registers in the embedded Native PHY IP
core. This interface provides direct access to the hard PCS registers on the device.
The transceiver reconfiguration interface complies with the Avalon Memory-Mapped (Avalon-MM)
specification defined in the Avalon Interface Specifications.
Related Information
• Transceiver Reconfiguration Signals on page 4-13
• Avalon Interface Specifications
Defines the Avalon Memory-Mapped (Avalon-MM) specification.
• Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver reconfiguration interface.
• Arria 10 Transceiver Registers
Detailed information about the Arria 10 transceiver registers.
Clocking and Reset Structure
The HMC Controller IP core has a single core clock domain and multiple transceiver-related clock
domains.
Your design must derive the external transceiver TX PLL reference clock, the RX CDR reference clock,
and the
REFCLKP
and
REFCLKN
input signals of the external HMC device from the same clock reference
source. This requirement ensures a 0 PPM difference between the receive and transmit clocks, as required
by the HMC specification.
3-4 External PLL Interface
UG-01152
2015.05.04
Altera Corporation Functional Description
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