Getting started with the hmc controller ip core, Getting started with the hmc controller ip core -1 – Altera Hybrid Memory Cube Controller User Manual
Page 10
Getting Started with the HMC Controller IP
Core
2
2015.05.04
UG-01152
The following information explains how to install, parameterize, and simulate the Altera Hybrid Memory
Cube Controller IP core.
Installing and Licensing IP Cores
The HMC Controller IP core is available with the Quartus II software in the Altera IP Library.
Specifying IP Core Parameters and Options
on page 2-2
The HMC Controller IP core supports the standard customization and generation process. This IP core is
not supported in Qsys.
HMC Controller IP Core Parameters
on page 2-3
The HMC Controller parameter editor provides the parameters you can set to configure the HMC
Controller IP core and simulation testbenches.
Files Generated for Altera IP Cores
on page 2-8
The Quartus II software generates multiple files during generation of your IP core variation.
Integrating Your IP Core in Your Design
To ensure the HMC Controller IP core functions correctly in hardware, you must connect additional
blocks to your IP core and assign device pins in order.
Simulating Altera IP Cores in other EDA Tools
on page 2-16
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
on page 2-18
Altera provides a testbench with the HMC Controller IP core.
Generating and Running the Testbench
on page 2-18
Related Information
•
HMC Controller IP Core Example Design
The HMC Controller example design provides an example of how to connect your IP core with an
external I
2
C master module and an external TX PLL.
•
Provides more information about generating an Altera IP core and integrating it in your Quartus II
project.
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