Altera Hybrid Memory Cube Controller User Manual
Page 23
Figure 2-8: Transceiver PLL Connections Example with PLL Feedback Compensation Scheme
Example connections between a full-width HMC Controller IP core and one ATX PLL IP core per
transceiver block. The PLL IP cores are in PLL Feedback Compensation Mode.
ATX PLL
ATX PLL
ATX PLL
ATX PLL
ATX PLL
ATX PLL
pll_locked
pll_powerdown
pll_powerdown
pll_powerdown
pll_locked
pll_locked
pll_cal_busy
pll_cal_busy
pll_cal_busy
HMC Controller IP Core
Txvr Block N
Txvr Block N+1
Txvr Block N+2
pll_locked
pll_cal_busy
pll_powerdown
tx_bonding_clocks (Channel 5)
tx_bonding_clocks (Channel 4)
tx_bonding_clocks (Channel 3) (Lane 15)
tx_bonding_clocks (Channel 2) (Lane 14)
tx_bonding_clocks (Channel 1) (Lane 13)
tx_bonding_clocks (Channel 0) (Lane 12)
tx_bonding_clocks (Channel 5) (Lane 11)
tx_bonding_clocks (Channel 4) (Lane 10)
tx_bonding_clocks (Channel 3) (Lane 9)
tx_bonding_clocks (Channel 2) (Lane 8)
tx_bonding_clocks (Channel 1) (Lane 7)
tx_bonding_clocks (Channel 0) (Lane 6)
tx_bonding_clocks (Channel 5) (Lane 5)
tx_bonding_clocks (Channel 4) (Lane 4)
tx_bonding_clocks (Channel 3) (Lane 3)
tx_bonding_clocks (Channel 2) (Lane 2)
tx_bonding_clocks (Channel 1) (Lane 1)
tx_bonding_clocks (Channel 0) (Lane 0)
tx_bonding_clocks[5:0]
tx_bonding_clocks[5:0]
tx_bonding_clocks[5:0]
You must connect the external PLL signals and the HMC Controller IP core transceiver TX PLL interface
signals according to the following rules:
HMC Controller Signal
Connects to TX PLL Signal
tx_bonding_clocks[5:0]
input signal
for HMC lane N
tx_bonding_clocks[5:0]
output vector of PLL IP core for the
transceiver block in which lane N is configured.
In the case of xN bonding, a single PLL connects to the xN
clock network and the
tx_bonding_clocks[5:0]
input pins
for HMC lanes in a different transceiver block from the
configured PLL receive the clock from the xN clock network.
pll_locked
input signal
Logical AND of the
pll_locked
output signals of the external
PLLs for all of the HMC lanes.
In the case of xN bonding, the single external PLL
pll_locked
output signal connects directly to the
pll_locked
input pin of
the HMC Controller IP core.
2-14
Adding the External PLL
UG-01152
2015.05.04
Altera Corporation
Getting Started with the HMC Controller IP Core